Provided is a SiC chemical vapor deposition apparatus including: a furnace body inside of which a growth space is formed; and a placement table which is positioned in the growth space and has a placement surface on which a SiC wafer is placed, in which the furnace body comprises a first hole which is positioned on an upper portion which faces the placement surface and through which a raw material gas is introduced into the growth space, a second hole which is positioned on a side wall of the furnace body and through which a purge gas flows into the growth space, a third hole which is positioned on the side wall of the furnace body at a lower position than the second hole and discharges the gases in the growth space, and a protrusion which is protrudes towards the growth space from a lower end of the second hole to adjust a flow of the raw material gas.

An atomizing apparatus for film formation, including: a raw-material container configured to accommodate a raw-material solution; a cylindrical member configured to spatially connect inside of the container to an outer unit, and disposed so a lower end of the cylindrical member does not touch a liquid surface of the solution in the container; an ultrasound generator having at least one ultrasound generation source; and a liquid tank where the ultrasound propagates to the raw-material solution through a middle solution. A center line of an ultrasound-emitting surface of the ultrasound generation source is designated u, the source is provided so an intersection P between line u and a plane containing a side wall surface of the cylindrical member and an extension thereof is located below a lower end point B of the cylindrical member. This provides an atomizing apparatus for film formation, enabling high-quality thin film formation with suppressed particle adhesion.

A mist generator may include a reservoir storing a solution, a plurality of ultrasonic vibrators, a mist delivery path, and a mist collector. The plurality of ultrasonic vibrators may be disposed under the reservoir and configured to apply ultrasonic vibration to the solution stored in the reservoir to generate mist of the solution in the reservoir. The mist delivery path may be configured to deliver the mist from an inside of the reservoir to an outside of the reservoir. The mist collector may be disposed above the solution in the reservoir, wherein an upper end of the mist collector may be connected to an upstream end of the mist delivery path, a lower end of the mist collector may include an opening, and a width of the mist collector may increase from the upper end toward the opening. The plurality of ultrasonic vibrators may be located directly under the opening.

Provided is a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×10.sup.14 cm.sup.−3 and less than or equal to 5×10.sup.16 cm.sup.−3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.