A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

An n.sup.--type drift layer is an n.sup.--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n.sup.--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n.sup.--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n.sup.--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n.sup.--type drift layer is at least 3×10.sup.16/cm.sup.3.

Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

A method of manufacturing a device including micrometer- or nanometer-range wires including a III-V compound, including, for each wire, the forming of at least a portion of the wire by a step of metal-organic vapor epitaxy including the injection into a reactor of a first precursor gas of the group-V element, of a second precursor gas of the group-III element, and of a third precursor gas of an additional element, dopant of the III-V compound, of a gas capable of obtaining a dopant concentration greater than 5.10.sup.19 atoms/cm.sup.3, for example, greater than 1.10.sup.20 atoms/cm.sup.3, in the wire portion in the case where the portion has a homogeneous dopant concentration.

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Disclosed herein are laser-assisted metal-organic chemical vapor deposition devices and methods of use thereof.

A light-emitting device according to an embodiment of the present disclosure includes: a semiconductor stack in which a first light reflection layer configured by an arsenic-based semiconductor layer including carbon as an impurity, an active layer, and a second light reflection layer are stacked; a first buffer layer provided on the first light reflection layer side of the semiconductor stack, having one face that faces the semiconductor stack and another face that is on an opposite side of the one face, and configured by a phosphorus-based semiconductor layer; and a second buffer layer provided at least between the first light reflection layer and the first buffer layer, and configured by an arsenic-based semiconductor layer including zinc or magnesium as an impurity.

The present disclosure describes epitaxial oxide field effect transistors (FETs). In some embodiments, a FET comprises: a substrate comprising an oxide material; an epitaxial semiconductor layer on the substrate; a gate layer on the epitaxial semiconductor layer; and electrical contacts. In some cases, the epitaxial semiconductor layer can comprise a superlattice comprising a first and a second set of layers comprising oxide materials with a first and second bandgap. The gate layer can comprise an oxide material with a third bandgap, wherein the third bandgap is wider than the first bandgap. In some cases, the epitaxial semiconductor layer can comprise a second oxide material with a first bandgap, wherein the second oxide material comprises single crystal A.sub.xB.sub.1-xO.sub.n, wherein 0<x<1.0, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.