Patent classifications
H01L21/02579
Semiconductor device comprising electron blocking layer
A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the first aluminum-containing layer and the active region, wherein the confinement layer includes a thickness smaller than the thickness of one of the barrier layers; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies in the electron blocking region.
METHOD FOR PRODUCING DOPED POLYCRYSTALLINE SEMICONDUCTOR LAYERS
The present invention relates to a method for producing highly doped polycrystalline semiconductor layers on a semiconductor substrate, wherein a first Si precursor composition comprising at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate; optionally a second Si precursor composition comprising at least one second dopant is applied to one or more other regions of the surface of the semiconductor substrate, where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; and the coated regions of the surface of the semiconductor substrate are each converted, so as to form polycrystalline silicon from the Si precursor. The invention further relates to the semiconductor obtainable by the method and to the use thereof, especially in the production of solar cells.
Method for epitaxial growth and device
A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
Seal material for air gaps in semiconductor devices
The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY
Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm.Math.cm.
STRUCTURES WITH DOPED SEMICONDUCTOR LAYERS AND METHODS AND SYSTEMS FOR FORMING SAME
Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.
Semiconductor devices and methods of manufacturing the same
A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.
SEMICONDUCTOR CRYSTAL SUBSTRATE, INFRARED DETECTOR, METHOD FOR PRODUCING SEMICONDUCTOR CRYSTAL SUBSTRATE, AND METHOD FOR PRODUCING INFRARED DETECTOR
A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
P-TYPE TRANSPARENT CONDUCTING NICKEL OXIDE ALLOYS
Disclosed herein is the formation of p-type transparent conducting oxides (TCO) having a structure of Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO. These structures disrupt the two-dimensional confinement of individual holes (the dominant charge carrier transport mechanism in pure NiO) creating three-dimensional hole transport by providing pathways for hole transfer in directions that are unfavorable in pure NiO. Forming these structures preserves NiO's transparency to visible light since the band gaps do not deviate significantly from that of pure NiO. Furthermore, forming Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO does not lead to hole trapping on O ions adjacent to Zn and Mg ions. The formation of these alloys will lead to creation of three-dimensional hole transport and improve NiO's conductivity for use as p-type TCO, without adversely affecting the favorable properties of pure NiO.
WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE WAFER
According to one embodiment, a wafer includes a silicon substrate including a first surface, and a nitride semiconductor layer provided on the first surface. The silicon substrate includes a plurality of first regions that can be distinguished from each other in an X-ray image of the wafer. The first regions are separated from an outer edge region of the silicon substrate. One of the first regions includes a plurality of first linear bodies along a first line direction. An other one of the first regions includes a plurality of second linear bodies along a second line direction. The second line direction crosses the first line direction.