The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures.

Provided is a SiC chemical vapor deposition apparatus including: a furnace body inside of which a growth space is formed; and a placement table which is positioned in the growth space and has a placement surface on which a SiC wafer is placed, in which the furnace body comprises a first hole which is positioned on an upper portion which faces the placement surface and through which a raw material gas is introduced into the growth space, a second hole which is positioned on a side wall of the furnace body and through which a purge gas flows into the growth space, a third hole which is positioned on the side wall of the furnace body at a lower position than the second hole and discharges the gases in the growth space, and a protrusion which is protrudes towards the growth space from a lower end of the second hole to adjust a flow of the raw material gas.

A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.

An atomizing apparatus for film formation, including: a raw-material container configured to accommodate a raw-material solution; a cylindrical member configured to spatially connect inside of the container to an outer unit, and disposed so a lower end of the cylindrical member does not touch a liquid surface of the solution in the container; an ultrasound generator having at least one ultrasound generation source; and a liquid tank where the ultrasound propagates to the raw-material solution through a middle solution. A center line of an ultrasound-emitting surface of the ultrasound generation source is designated u, the source is provided so an intersection P between line u and a plane containing a side wall surface of the cylindrical member and an extension thereof is located below a lower end point B of the cylindrical member. This provides an atomizing apparatus for film formation, enabling high-quality thin film formation with suppressed particle adhesion.

Provided is a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

A manufacturing method of a nitride semiconductor device includes: introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region; forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region; and performing an anneal treatment in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer.

A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.