The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.

Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.

An n.sup.--type drift layer is an n.sup.--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n.sup.--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n.sup.--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n.sup.--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n.sup.--type drift layer is at least 3×10.sup.16/cm.sup.3.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

A method for manufacturing a semiconductor structure, a semiconductor structure, and a capacitor structure are provided. The method includes: providing a substrate, a plurality of blind holes or grooves being provided in a surface of the substrate; forming filling layers in the plurality of blind holes or grooves, top surfaces of the filling layers being flush with a top surface of the substrate; and forming a cap layer on the top surfaces of the filling layers and the top surface of the substrate, in which the cap layer includes at least a film-stacked structure, the film-stacked structure includes a first cap film and a second cap film, and a doping material source of the first cap film is different from a doping material source of the second cap film.

InGaN offers a route to high efficiency overall water splitting under one-step photo-excitation. Further, the chemical stability of metal-nitrides supports their use as an alternative photocatalyst. However, the efficiency of overall water splitting using InGaN and other visible light responsive photocatalysts has remained extremely low despite prior art work addressing optical absorption through band gap engineering. Within this prior art the detrimental effects of unbalanced charge carrier extraction/collection on the efficiency of the four electron-hole water splitting reaction have remained largely unaddressed. To address this growth processes are presented that allow for controlled adjustment and establishment of the appropriate Fermi level and/or band bending in order to allow the photochemical water splitting to proceed at high rate and high efficiency. Beneficially, establishing such material surface charge properties also reduces photo-corrosion and instability under harsh photocatalysis conditions.