A semiconductor structure comprising III-N materials, includes: a support substrate; a main layer of III-N material, the main layer comprising a first section disposed on the support substrate and a second section disposed on the first section; an inter-layer of III-N material, disposed between the first section and the second section in order to compress the second section of the main layer, wherein the structure's inter-layer consists of a lower layer disposed on the first section and an upper layer disposed on the lower layer and formed by a superlattice.

Provided is an n-type GaN crystal, in which a donor impurity contained at the highest concentration is Ge, and which has a room-temperature resistivity of lower than 0.03 Ω.Math.cm and a (004) XRD rocking curve FWHM of less than 20 arcsec. The n-type GaN crystal has two main surfaces, each having an area of 2 cm.sup.2 or larger. One of the two main surfaces can have a Ga polarity and can be inclined at an angle of 0° to 10° with respect to a (0001) crystal plane. Further, the n-type GaN crystal can have a diameter of 20 mm or larger.

The present invention discloses a metal oxide (MO) semiconductor, which is implemented by respectively doping at least an oxide of rare earth element R and an oxide of rare earth element R′ into an indium-containing MO semiconductor to form an In.sub.xM.sub.yR.sub.nR′.sub.mO.sub.z semiconductor. According to the present invention, the extremely high oxygen bond breaking energy in the oxide of rare earth element R is used to effectively control the carrier concentration in the semiconductor, and a charge transportation center can be formed by using the characteristic that the radius of rare earth ions is equivalent to the radius of indium ions, so that the electrical stability of the semiconductor is improved. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.

An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 Å and 3.21 Å, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

A semiconductor structure and a manufacturing method therefor are provided by embodiments of the present application. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. In the second buffer layer, by decreasing a doping concentration of the transition metal or not doping intentionally the transition metal, a tailing effect is avoided and current collapse is prevented. By doping periodically C in the buffer layer, C may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced.

A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.

A manufacturing method of a nitride-based semiconductor light-emitting element includes: forming an n-type nitride-based semiconductor layer; forming, on the n-type nitride-based semiconductor layer, a light emission layer including a nitride-based semiconductor; forming, on the light emission layer in an atmosphere containing a hydrogen gas, a p-type nitride-based semiconductor layer while doping the p-type nitride-based semiconductor layer with a p-type dopant at a concentration of at least 2.0×10.sup.18 atom/cm.sup.3; and annealing the p-type nitride-based semiconductor layer at a temperature of at least 800 degrees Celsius in an atmosphere not containing hydrogen. In this manufacturing method, a hydrogen concentration of the p-type nitride-based semiconductor layer after the annealing is at most 5.0×10.sup.18 atom/cm.sup.3 and at most 5% of the concentration of the p-type dopant, and a hydrogen concentration of the light emission layer is at most 2.0×10.sup.17 atom/cm.sup.3.

A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, an aurum layer, and an electroplating copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.

A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.