It is an object of the present invention to provide a silicon carbide substrate having a low defect density that does not contaminate a process device and a silicon carbide semiconductor device including the silicon carbide substrate. A silicon carbide substrate according to the present invention is a silicon carbide substrate including: a substrate inner portion; and a substrate outer portion surrounding the substrate inner portion, wherein non-dopant metal impurity concentration of the substrate inner portion is 110.sup.16 cm.sup.3 or more, and a region of the substrate outer portion at least on a surface side thereof is a substrate surface region in which the non-dopant metal impurity concentration is less than 110.sup.16 cm.sup.3.

A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

The invention relates to a process for manufacturing a heterojunction electronic component provided with an embedded barrier layer, the process comprising: depositing by epitaxy, in a vapour phase epitaxial growth chamber with an atmosphere exhibiting a first nonzero ammonia concentration, of a GaN precursor layer of the embedded barrier layer, comprising a first layer doped with a Mg or Fe dopant; placing, while maintaining the substrate in the chamber, the atmosphere at a second ammonia concentration at most equal to a third of the first concentration, in order to remove an upper part of the precursor layer; and then after the removal of the said upper part, while maintaining the substrate in the chamber, depositing by epitaxy of a layer of semiconductor material of the heterojunction electronic component to be manufactured, the said precursor layer then forming the embedded barrier layer under the said layer of semiconductor material.

A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes: controlling a temperature of a sputtering target, and modulating between a gallium-rich condition and a gallium-lean condition, wherein the gallium-rich condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, and wherein the gallium-lean condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value. Some embodiments include a load lock configured to load a substrate wafer into the system and remove the GaN structure from the system; and a plurality of deposition chambers, wherein the plurality of deposition chambers includes a GaN-deposition chamber configured to grow at least the first GaN layer on a template that includes the substrate wafer.

A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

An apparatus for fabricating a thin film is provided. The apparatus includes a tube including one end and another end, a first heater supplying heat to a first region, adjacent to the one end, of the tube, a second heater supplying heat to a second region, adjacent to the another end, of the tube and disposed in parallel to the first heater along the tube, a gas inlet through which a source gas is supplied to the one end of the tube, and a gas outlet through which the source gas is exhausted from the another end of the tube.

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. Also disclosed is single crystal Mg.sub.xGe.sub.1-xO.sub.2-x, with x having a value of 0?x<1. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a dopant chosen from Ga, Al, Li.sup.+, N.sup.3+. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a p-type conductivity.

A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.