On a front surface of an n.sup.+-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n.sup.+-type buffer layer, an n.sup.-type drift layer, and a p.sup.+-type anode layer sequentially formed by epitaxial growth. The n.sup.+-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n.sup.+-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n.sup.+-type buffer layer.

Low resistivity, wrap-around contact structures are provided in nanosheet devices, vertical FETs, and FinFETs. Such contact structures are obtained by delivering dopants to source/drain regions using a highly conformal, doped metal layer. The conformal, doped metal layer may be formed by ALD or CVD using a titanium tetraiodide precursor. Dopants within the conformal, doped metal layer are delivered during the formation of wrap-around metal silicide or metal germano-silicide regions. Dopant segregation at silicide/silicon interfaces or germano-silicide/silicon interfaces reduces contact resistance in the wrap-around contact structures. A contact metal layer electrically communicates with the wrap-around contact structures.

A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.

A semiconductor device substrate including: a substrate; a buffer layer which is provided on the substrate and made of a nitride semiconductor; and a device active layer which is formed of a nitride semiconductor layer provided on the buffer layer, the semiconductor device substrate in that the buffer layer includes: a first region which contains carbon and iron; a second region which is provided on the first region and has average concentration of iron lower than that in the first region and average concentration of carbon higher than that in the first region, and the average concentration of the carbon in the second region is lower than the average concentration of the iron in the first region. The semiconductor device substrate which can suppress a transverse leak current in a high-temperature operation of a device while suppressing a longitudinal leak current and can inhibit a current collapse phenomenon is provided.

Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 110.sup.6 .Math.cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 110.sup.17/cm.sup.3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1, 0y1).

The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.

A method of synthesizing catalyst doped ZnS nanostructures including preparing a silicon substrate by vacuum depositing a metal catalyst nanostructure on an ultrathin silicon oxide layer, doping a zinc sulfide (ZnS) nanostructure with a catalyst of the metal catalyst nanostructure including at least one of gold (Au), manganese (Mn), and tin (Sn), and modulating ZnS intrinsic defects by the concentration of the catalyst and the size of the ZnS and metal catalyst nanostructures, in which the catalyst is dissolved in a nanowire of the ZnS nanostructure during growth, the concentration of the catalyst in the nanowire is dependent on the size of the catalyst, and the doping is tuned by growth conditions.

A method including the following successive steps: a) forming, on a surface of a support substrate, a first layer made of a material selected from among a lamellar dichalcogenide or a lamellar chalcogenide including a stack of sheets; b) forming, by physical vapor deposition on the side of said surface of the support substrate, a second layer made of a first III-N semiconductor material coating the first layer; and c) carrying out a thermo-chemical treatment of the first layer resulting, in the first layer, in a conversion of van der Waals bonds between the sheets of the first layer into covalent bonds.

A large Group III nitride crystal of high quality with few defects such as a distortion, a dislocation, and warping is produced by vapor phase epitaxy. A method for producing a Group III nitride crystal includes: a first Group III nitride crystal production process of producing a first Group III nitride crystal 1003 by liquid phase epitaxy; and a second Group III nitride crystal production process of producing a second Group III nitride crystal 1004 on the first crystal 1003 by vapor phase epitaxy. In the first Group III nitride crystal production process, the surfaces of seed crystals 1003a (preliminarily provided Group III nitride) are brought into contact with an alkali metal melt, a Group III element and nitrogen are cause to react with each other in a nitrogen-containing atmosphere in the alkali metal melt, and the Group III nitride crystals are bound together by growth of the Group III nitride crystals grown from the seed crystals 1003a to produce a first crystal 1003.

The invention relates to a process for manufacturing a heterojunction electronic component provided with an embedded barrier layer, the process comprising: depositing by epitaxy, in a vapour phase epitaxial growth chamber with an atmosphere exhibiting a first nonzero ammonia concentration, of a GaN precursor layer of the embedded barrier layer, comprising a first layer doped with a Mg or Fe dopant; placing, while maintaining the substrate in the chamber, the atmosphere at a second ammonia concentration at most equal to a third of the first concentration,order to remove an upper part of the precursor layer; and then after the removal of the said upper part, while maintaining the substrate in the chamber, depositing by epitaxy of a layer of semiconductor material of the heterojunction electronic component to be manufactured, the said precursor layer then forming the embedded barrier layer under the said layer of semiconductor material.