A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

A manufacturing method of a display apparatus including preparing a substrate, forming an amorphous silicon layer on the substrate, cleaning the amorphous silicon layer with hydrofluoric acid, crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and forming a metal layer directly on the polycrystalline silicon layer.

A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

Embodiments of the present disclosure relate to methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a plasma-enhanced chemical vapor deposition (PECVD) process. In particular, the methods described herein utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods described herein provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

Provided are a laser annealing apparatus and a method of manufacturing a substrate having a poly-Si layer using the laser annealing apparatus. The laser annealing apparatus includes a laser beam source that emits a linearly polarized laser beam, a polygon mirror that rotates around a rotation axis and reflects the laser beam emitted from the laser beam source, a first Kerr cell disposed on a laser beam path between the laser beam source and the polygon mirror, and a first optical element that directs the laser beam reflected by the polygon mirror toward an amorphous Si layer where the laser beam is irradiated upon the amorphous Si layer.

A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 μm to about 2 μm, and a length of the channel of the third transistor is in a range of about 1 μm to about 2.5 μm.

A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si.sub.1-yGe.sub.y, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si.sub.1-xGe.sub.x, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.

A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately-above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately-above the internal interface is lower than immediately-below the internal interface and (b): a laterally-discontinuous insulative oxide. Other embodiments, including method, are disclosed.