A film forming method for forming a silicon film having a step coverage on a substrate having a recess in a surface of the substrate, the film forming method comprising: forming a silicon film such that a film thickness on an upper portion of a side wall of the recess is thicker than a film thickness on a lower portion of the side wall of the recess by supplying a silicon-containing gas to the substrate; and etching a portion of the silicon film conformally by supplying an etching gas to the substrate, wherein the act of forming the silicon film and the act of etching the portion of the silicon film are performed a number of times which is determined depending on the step coverage.

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si.sub.3N.sub.4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO.sub.2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO.sub.2. The two SiO.sub.2 layers together form a blocking oxide layer.

A display device includes a first support plate and a pixel region over the first support plate. A thin film transistor (TFT) structure is disposed over the first support plate and associated with the pixel region. The TFT structure includes a first metal layer over the first support plate. The first metal layer includes a gate. A silicon layer is disposed over the gate. A second metal layer is disposed over the silicon layer. The second metal layer includes a source and a drain covering a first portion of the silicon layer. An amorphous silicon layer is disposed over at least a portion of the second metal layer and a second portion of the silicon layer.

A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is surrounded by the dielectric layer. A metal layer is disposed over the dielectric layer. The second segment of the fin structure is surrounded by the metal layer. The dielectric layer has a greater nitrogen content than the metal layer. The first segment of the fin structure also has a first side surface that is rougher than a second side surface of the second segment of the fin structure.

In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

A method of forming a crystalline silicon film includes forming a first amorphous silicon film on a substrate, forming a crystal nucleation film in which crystal nuclei of silicon are formed by performing a first annealing on the substrate having the first amorphous silicon film formed thereon, performing etching with an etching gas, forming a second amorphous silicon film on the crystal nuclei remaining after the etching, and forming a crystalline silicon film by performing a second annealing on the substrate after the forming of the second amorphous silicon film to grow the crystal nuclei.

The invention relates to a process for fabricating a solar cell. The process comprises depositing a layer of amorphous silicon on a substrate using physical vapour deposition, said substrate being a layer of a dielectric disposed on a silicon wafer. The amorphous silicon is then annealed so as to generate a layer of polycrystalline silicon on the substrate.

Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).