Provided herein is a method of manufacturing a memory device. The method of manufacturing the memory device includes: forming a compensation layer over the channel layer, wherein an incubation time used for a nucleation of the compensation layer is shorter than an incubation time of the channel layer; and performing a heat treatment process for crystallizing the channel layer.

A workpiece conveyance apparatus having: a conveyance path on which the workpiece moves; a gas flotation section that gas-floats the workpiece over the conveyance path; a movable holding section that holds the workpiece to move on the conveyance path along with the workpiece; and a treatment region conveyance path that is located on the conveyance path, and has a treatment region where predetermined treatment for the workpiece is performed, wherein the movable holding section has at least two or more holding sections along a movement direction of the conveyance path, each of the holding sections is capable of switching between release of holding and holding for the workpiece during movement of the workpiece, operation for releasing holding of the workpiece by the holding section on the treatment region conveyance path, and holding the workpiece on the conveyance path other than the treatment region conveyance path.

A semiconductor substrate includes a single crystal Ga.sub.2O.sub.3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga.sub.2O.sub.3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga.sub.2O.sub.3-based substrate.

A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

Methods for low-temperature formation of one or more thin-film semiconductor structures on a substrate that include the steps of, forming a (poly)silane layer over a substrate, transforming one or more parts of the (poly)silane layer in one or more thin-film solid-state semiconductor structures, by exposing the one or more parts with light from an

Described herein are precursors and methods for forming silicon-containing films. In one aspect, there is provided an aza-polysilane precursor comprising at least two Si—N bonds, at least one Si—Si bond, and at least two SiH.sub.2 groups represented by the following Formula IA, IB and IC: ##STR00001##
wherein R.sup.1 and R.sup.2 are independently selected from a linear or branched C.sub.1 to C.sub.10 alkyl group, a linear or branched C.sub.3 to C.sub.10 alkenyl group, a linear or branched C.sub.3 to C.sub.10 alkynyl group, C.sub.3 to C.sub.10 cyclic alkyl group, C.sub.3 to C.sub.10 hetero-cyclic alkyl group, a C.sub.5 to C.sub.10 aryl group, and a C.sub.3 to C.sub.10 hetero-aryl group, a C.sub.2 to C.sub.10 dialkylamino group, a C.sub.3 to C.sub.10 cyclic alkylamino group; R.sup.3 and R.sup.4 are independently selected from hydrogen, a linear or branched C.sub.1 to C.sub.10 alkyl group, a linear or branched C.sub.2 to C.sub.10 alkenyl group, a linear or branched C.sub.2 to C.sub.10 alkynyl group, C.sub.3 to C.sub.10 cyclic alkyl group, C.sub.3 to C.sub.10 hetero-cyclic alkyl group, a C.sub.5 to C.sub.10 aryl group, and a C.sub.3 to C.sub.10 hetero-aryl group, a C.sub.2 to C.sub.10 dialkylamino group, a C.sub.3 to C.sub.10 cyclic alkylamino group; wherein R.sup.1 in Formula IA cannot both be methyl, R.sup.1 and R.sup.2 in Formula IB cannot both be iso-propyl, tert-butyl, and bezenyl and R.sup.3 and R.sup.4 cannot both be methyl and phenyl.

A manufacturing method of array substrates, an array substrate, and a display panel are disclosed. The manufacturing method of the array substrate includes: forming a first electrode and a gate electrode on a substrate in sequence; forming an insulation layer, a semiconductor layer and a dielectric layer on the substrates in sequence and forming a first through hole, a second through hole and a third through hole; forming a source electrode, a drain electrode, a second electrode and a third electrode on the dielectric layer, wherein the source electrode and the drain electrode connect to the semiconductor layer respectively, the second electrode connects to the first electrode and the third electrode connects with the drain electrode. In this way, the number of the masks needed during the manufacturing process is decreased. In addition, the manufacturing process is simplified and the cost is reduced.

A method includes following steps. An interconnect structure is formed over a first transistor. A dielectric layer is formed over the interconnect structure. The dielectric layer is etched to form holes in the dielectric layer. An amorphous layer is deposited in the holes of the dielectric layer and on a top surface of the dielectric layer. The amorphous layer is crystallized into a polycrystalline layer. A second transistor is formed on the polycrystalline layer.

Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.

The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

To provide a crystalline oxide semiconductor film, an ion is made to collide with a target including a crystalline In—Ga—Zn oxide, thereby separating a flat-plate-like In—Ga—Zn oxide in which a first layer including a gallium atom, a zinc atom, and an oxygen atom, a second layer including an indium atom and an oxygen atom, and a third layer including a gallium atom, a zinc atom, and an oxygen atom are stacked in this order; and the flat-plate-like In—Ga—Zn oxide is irregularly deposited over a substrate while the crystallinity is maintained.