A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

A method of forming a multitude of vertical NAND memory cells, includes, in part, forming a multitude of insulating materials on a silicon substrate, forming a trench in the insulating materials to expose a surface of the silicon substrate, depositing a layer of polysilicon along the sidewalls of the trench, filling the trench with oxide, forming a metal layer above the trench, and forming a mono-crystalline channel for the NAND memory cells by applying a voltage between the silicon substrate and the metal layer to cause the polysilicon sidewalls to melt. The melted polysilicon sidewalls is enable to recrystallize into the mono-crystalline channel.

A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO.sub.3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.

A film formation apparatus includes a stage, a heater, a mist supply source, a superheated vapor supply source, and a delivery device. The stage is configured to allow a substrate to be mounted thereon. The heater is configured to heat the substrate. The mist supply source is configured to supply mist of a solution that comprises solvent and a film material dissolved in the solvent. The superheated vapor supply source is configured to supply a superheated vapor of a same material as the solvent. The delivery device is configured to deliver the mist and the superheated vapor toward a surface of the substrate to grow a film containing the film material on the surface of the substrate.

Semiconductor device is provided. The semiconductor device includes a substrate and a fin on the substrate. The fin includes channel layers stacked along a normal direction of a substrate surface. The channel layers includes a first channel layer and a second channel layer under the first channel layer, and the second channel layer has recessed sidewalls with respect to corresponding sidewalls of the first channel layer. The semiconductor device further includes a gate structure, disposed around each of the first channel layer and the second channel layer; and a doped source/drain layer in the fin on two sides of the gate structure. The doped source/drain layer is respectively connected to the second channel layer and the first channel layer.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.

A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

The present application provides a method for manufacturing a monocrystalline silicon sheet, including: cutting a monocrystalline silicon rod along a radial or an axial direction of the monocrystalline silicon rod to obtain a monocrystalline silicon substrate; etching a porous silicon structure on a top surface and a bottom surface of the monocrystalline silicon substrate by wet etching; depositing a monocrystalline silicon thin layer on the porous silicon structure by chemical vapor deposition, so that a thickness of the monocrystalline silicon thin layer reaches a predetermined value; and striping the monocrystalline silicon thin layer from the porous silicon structure to obtain the monocrystalline silicon sheet. In the present application, the production capacity of directly manufacturing a single crystal silicon wafer by a chemical vapor deposition method can be improved, and a process for manufacturing a silicon wafer is combined with the process of a diffusion emitter conventionally belonging to cell manufacturing, so that a manufacturing cost of a solar monocrystalline silicon cell is significantly reduced.

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.