A vertical nitride semiconductor device includes an n-type aluminum nitride single-crystal substrate having an Si content of 3×10.sup.17 to 1×10.sup.20 cm.sup.−3 and a dislocation density of 10.sup.6 cm.sup.−2 or less. An ohmic electrode layer is formed on an N-polarity side of the n-type aluminum nitride single-crystal substrate.

A semiconductor device which can reduce power consumption and a method for manufacturing the same are provided. A semiconductor device comprises an Si (silicon) substrate, an SIC (silicon carbide) layer formed on the surface of the Si substrate, an AIN (aluminum nitride) layer formed on the surface of the SiC layer, an n-type GaN (gallium nitride) layer formed on the surface of the AIN layer, a first electrode formed at the surface side of the GaN layer, and a second electrode formed at the reverse face side of the Si substrate 1. The magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.

A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.

Various embodiments provide Molten Target Sputtering (MTS) methods and devices. The various embodiments may provide increases in the kinetic energy, increases in the energy latency, and/or increases in the flux density of molecules for better crystal formation at low temperature operation. The various embodiment MTS methods and devices may enable the growth of a single crystal Si.sub.1-xGe.sub.x film on a substrate heated to less than about 500° C. The various embodiment MTS methods and devices may provide increases in the kinetic energy, increases in the energy latency, and/or increases in the flux density of molecules without requiring the addition of extra systems.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

There is provided a method of manufacturing a semiconductor device, including forming a seed layer on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a halogen-based first processing gas to the substrate; supplying a non-halogen-based second processing gas to the substrate; and supplying a hydrogen-containing gas to the substrate. Further, the method further includes forming a film on the seed layer by supplying a third processing gas to the substrate.

A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed.

Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below:

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In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.