As one embodiment, the present invention provides a method for growing a β-Ga.sub.2O.sub.3-based single crystal film by using HYPE method. The method includes a step of exposing a Ga.sub.2O.sub.3-based substrate to a gallium chloride-based gas and an oxygen-including gas, and growing a β-Ga.sub.2O.sub.3-based single crystal film on a principal surface of the Ga.sub.2O.sub.3-based substrate at a growth temperature of not lower than 900° C.

A method for forming alpha-gallium oxide (α-Ga.sub.2O.sub.3) on GaN-compatible substrates uses an epitaxial deposition process comprising (a) forming about one monolayer of wurtzite gallium nitride (w-GaN) on the substrate; (b) reacting the said monolayer of w-GaN with an oxygen precursor to form about one monolayer of α-Ga.sub.2O.sub.3 on the substrate; (c) repeating steps (a) and (b) to form one or more additional monolayers of α-Ga.sub.2O.sub.3 on the substrate.

A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

Provided is an SiC composite substrate 10 having a monocrystalline SiC layer 12 on a polycrystalline SiC substrate 11, wherein: some or all of the interface at which the polycrystalline SiC substrate 11 and the monocrystalline SiC layer 12 are in contact is an unmatched interface I.sub.12/11 that is not lattice-matched; the monocrystalline SiC layer 12 has a smooth obverse surface and has, on the side of the interface with the polycrystalline SiC substrate 11, a surface that has more pronounced depressions and projections than the obverse surface; and the close-packed plane (lattice plane 11p) of the crystals of the polycrystalline SiC in the polycrystalline SiC substrate 11 is randomly oriented with reference to the direction of a normal to the obverse surface of the monocrystalline SiC layer 12. The present invention improves the adhesion between the polycrystalline SiC substrate and the monocrystalline SiC layer.

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side surface of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

A method for producing a MEMS device comprises fabricating a first semiconductor layer and selectively depositing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer comprises a first part composed of monocrystalline semiconductor material and a second part composed of polycrystalline semiconductor material. The method furthermore comprises structuring at least one of the semiconductor layers, wherein the monocrystalline semiconductor material of the first part and underlying material of the first semiconductor layer form a spring element of the MEMS device and the polycrystalline semiconductor material of the second part and underlying material of the first semiconductor layer form at least one part of a comb drive of the MEMS device.

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Disclosed is a method for manufacturing a monocrystalline semiconductor material of the nitride of a group 13 element, comprising a step of depositing at least one separation layer comprising an element M selected among Ge, Zr, Y, Si, Se, Sc, Mg, In, W, La, Ti, Ta and Hf, by epitaxial growth on a starting substrate; characterised in that an interface layer of formula M.sub.vAl.sub.xO.sub.yN.sub.z is deposited between the starting substrate and the separation layer, wherein: - the atomic indices x and z are greater than 0 and less than or equal to 1; and, - the atomic indices v and y are between 0 and 1; and - the sum y+z is greater than 0.9 and less than or equal to 1.5; and - the sum v+y is greater than or equal to 0.3 and less than or equal to 1.