A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

Conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures. A plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of a plurality of gate structures and co-planar with an uppermost surface of a plurality of conductive trench contact structures. A dielectric layer is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers. The dielectric layer has a planar uppermost surface. An opening is in the dielectric layer, the opening exposing one of the plurality of gate structures or one of the plurality of conductive trench contact structures. A conductive via is in the opening. The conductive via has an uppermost surface co-planar with the planar uppermost surface of the dielectric layer.

A method for selectively etching layers of a first material with respect to layers of a second material in a stack is provided. The layers of the first material are partially etched with respect to the layers of the second material. A deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions covering the layers of the first material, the selective depositing comprising providing a first reactant, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant and selectively deposits on the layers of the second material with respect to the layers of the first material. The layers of the first material are selectively etched with respect to the layers of the second material.

Provided are a method for preparing an InGaN-based epitaxial layer on a Si substrate (12), as well as a silicon-based InGaN epitaxial layer prepared by the method. The method may include the steps of: 1) directly growing a first InGaN-based layer (11) on a Si substrate (12); and 2) growing a second InGaN-based layer on the first InGaN-based layer (11).

A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer.

An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

A device, such as a light-emitting device, e.g. a laser device, comprising: a plurality of group III-V semiconductor NWs grown on one side of a graphitic substrate, preferably through the holes of an optional hole-patterned mask on said graphitic substrate; a first distributed Bragg reflector or metal mirror positioned substantially parallel to said graphitic substrate and positioned on the opposite side of said graphitic substrate to said NWs; optionally a second distributed Bragg reflector or metal mirror in contact with the top of at least a portion of said NWs; and wherein said NWs comprise aim-type doped region and a p-type doped region and optionally an intrinsic region there between.