A semiconductor device includes first and second sheet patterns spaced apart from each other on a first region of the substrate, a first gate electrode extending between the first and second sheet patterns, third and fourth sheet patterns spaced apart from each other on a second region of the substrate, and a second gate electrode extending between the third and fourth sheet patterns. The first gate electrode includes a first work function controlling film, which is between the first and second sheet patterns, and a first filling conductive film on the first work function controlling film. The second gate electrode includes a second work function controlling film, which is between the third and fourth sheet patterns, and a second filling conductive film on the second work function controlling film. A distance between the third and fourth sheet patterns is greater than a distance between the first and second sheet patterns.

Presented herein are gas permeable, ultrathin, stretchable epidermal electronic devices and related methods enabled by self-assembled porous substrates and conductive nanostructures. Efficient and scalable breath figure method is employed to introduce the porous skeleton and then silver nanowires (AgNWs) are dip-coated and heat-pressed to offer electric conductivity. The resulting film has a transmittance of 61%, sheet resistance of 7.3 Ω/sq, and water vapor permeability of 23 mg cm.sup.−2 h.sup.−1. With AgNWs embedded below the surface of the polymer, the electrode exhibits excellent stability with the presence of sweat and after long-term wear. The present subject matter demonstrates the potential of the electrode for wearable applications—skin-mountable biopotential sensing for healthcare and textile-integrated touch sensing for human-machine interfaces. The electrode can form conformal contact with human skin, leading to low skin-electrode impedance and high-quality biopotential signals. In addition, the textile electrode can be used in a self-capacitance wireless touch sensing system.

A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.

A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.

Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

Disclosed is a semiconductor device including: a substrate including a first active pattern separated into a pair of first active patterns by a trench; a device isolation layer filling the trench; first source/drain patterns on the first active pattern; a first channel pattern connected to the first source/drain patterns and including semiconductor patterns; a first dummy gate electrode that extends while being adjacent to a first sidewall of the trench; a gate electrode that is spaced apart in the first direction from the first dummy gate electrode and extends while running across the first channel pattern, a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending between the gate electrode and the first dummy gate electrode. A top surface of the separation pattern is at a same level as that of the gate capping pattern.

A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Embodiments include a nanoFET device and method for forming the same, the nanoFET having channel regions which have been thinned during a gate replacement process to remove etching residue. In some embodiments, the channel regions become dog bone shaped. In some embodiments, the ends of the channel regions have vertical protrusions or horns resulting from a previous trimming process which is performed prior to depositing sidewall spacers.

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.