A method for obtaining metallic carbon nanotubes is provided. An insulating substrate comprising hollow portions and non-hollow portions is provided. A plurality of electrodes is formed on a surface of the non-hollow portions. A plurality of carbon nanotubes is formed on a surface of the insulating substrate, and the carbon nanotubes stretch across the hollow portions. The insulating substrate, the plurality of electrodes and the carbon nanotubes are placed into a cavity, and the cavity is evacuated. A voltage is applied between any two electrodes, and photos of carbon nanotubes suspended between the two electrodes are taken. In the photo, darker ones are semiconducting carbon nanotubes, and brighter ones are metallic carbon nanotubes. Finally, the semiconducting carbon nanotubes are removed.

A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Manufacturing an electrical device including providing a substrate having a surface and forming a radiofrequency field effect transistor on the surface, including forming a CNT layer on the surface and depositing a pin-down layer on the CNT layer. The pin-down layer is patterned to form separate pin-down anchor layers. A first portion of the CNT layer, located in-between the pin-down anchor layers and second portions of the CNT layer are covered by the pin-down anchor layers. For cross-sections in a direction perpendicular to a common alignment direction of the electrically conductive aligned carbon nanotubes in the first portion of the CNT layer the electrically conductive aligned carbon nanotubes have an average linear density in a range from 20 to 120 nanotubes per micron along the cross-sections, and at least 40 percent of the electrically conductive aligned carbon nanotubes are discrete from any carbon nanotubes of the CNT layer. A radiofrequency field effect transistor having such a CNT layer and pin-down anchor layers is also disclosed.

A method of forming a memory device includes the following steps. A plurality of carbon nanotubes are formed over a substrate as a first electrode. An insulating layer is formed over the carbon nanotubes. A graphene is formed over the insulating layer as a second electrode separated from the first electrode by the insulating layer.

A method for manufacturing a semiconductor device includes forming a plurality of pillars on a substrate. Each pillar of the plurality of pillars includes a silicon germanium portion. In the method, a layer of germanium oxide is deposited on the plurality of pillars, and a thermal annealing process is performed to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes. Each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion. The method also includes exposing top surfaces of each of the silicon germanium core portions, and selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

A method for manufacturing a nanostructure composite material includes a step of preparing an inorganic material nanostructure, and a step of embedding an organic material to the inorganic material nanostructure so as to form the nanostructure composite material. In addition, a nanostructure composite material is also provided.

Stacked SiGe nanotubes and techniques for the fabrication thereof are provided. In one aspect, a method of forming a SiGe nanotube stack includes: forming Si and SiGe layers on a wafer, one on top of another, in an alternating manner; patterning at least one fin in the Si and SiGe layers; depositing an oxide material onto the at least one fin; and annealing the at least one fin under conditions sufficient to diffuse Ge atoms from the SiGe layers along an interface between the oxide material and the Si and SiGe layers to form at least one vertical stack of SiGe nanotubes surrounding Si cores. A SiGe nanotube device and method for formation thereof are also provided.

A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalls from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalls. The lateral semiconductor nanotube shell comprises a hexagonal shape.