Patent classifications
H01L21/02628
Coating liquid for forming metal oxide film, oxide film, field-effect transistor, and method for producing the same
A coating liquid for forming a metal oxide film, the coating liquid including: a metal source, which is at least one selected from the group consisting of inorganic salts, oxides, hydroxides, metal complexes, and organic acid salts; at least one alkali selected from the group consisting of organic alkalis and inorganic alkalis; and a solvent.
Laser Fabrication of Lead Selenide Thin Film
A laser sintering deposition method for disposing lead selenide onto a substrate. The method includes: wet-milling a lead selenide ingot mixed with methanol into a colloidal slurry containing nanocrystals; separating the colloidal slurry into nanocrystal particles and the methanol; depositing the nanocrystal particles to a substrate; and emitting coherent infrared light onto the nanocrystal particles for fusing into a lead selenide crystalline film. Afterwards, the lead selenide film can be exposed to oxygen to form a lead selenite layer, and subsequently to iodine gas to produce a lead iodide layer onto the lead selenite layer.
MANUFACTURING METHOD OF ITO THIN FILM BASED ON SOLUTION METHOD
A manufacturing method of an indium tin oxide (ITO) thin film based on a solution method is disclosed. The manufacturing method includes: a step of providing an array substrate; a step of obtaining a dispersion solution by mixing ITO grains, an organic small molecule phase transfer agent, and an N-chlorosuccinimide (NCs) solution; a step of obtaining uniformly assembled ITO grains by coating the dispersion solution onto a passivation layer and baking to remove the organic small molecule phase transfer agent; and a step of obtaining the ITO thin film by annealing at an inert atmosphere to refine the ITO grains.
THIN FILM TRANSISTORS HAVING A SPIN-ON 2D CHANNEL MATERIAL
Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.
Film forming method and crystalline multilayer structure
The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.
A METHOD FOR PRODUCING A CRYSTALLINE OXIDE SEMICONDUCTOR FILM AND A GALLIUM OXIDE FILM, AND A METHOD FOR PRODUCING A VERTICAL SEMICONDUCTOR DEVICE
A method for producing a crystalline oxide semiconductor film in which, a crystalline oxide semiconductor layer and a light absorbing layer are laminated on a substrate, the light absorbing layer is irradiated with light to decompose the light absorbing layer and separate the crystalline oxide semiconductor layer and the substrate to produce a crystalline oxide semiconductor film. This provides a method for industrially advantageously producing a crystalline oxide semiconductor film, for example, a crystalline oxide semiconductor film useful for a semiconductor device (particularly a vertical element).
APPARATUS, SYSTEMS, AND METHODS FOR TUNING THE STRUCTURE, CONDUCTIVITY, AND/OR WETTABILITY OF LASER INDUCED GRAPHENE FOR A VARIETY OF FUNCTIONS INCLUDING MULTIPLEXED OPEN MICROFLUIDIC ENVIRONMENTAL BIOSENSING AND ENERGY STORAGE DEVICES
Apparatus, systems, and methods for tuning the structure, conductivity, and/or wettability of laser induced graphene for a variety of functions including but not limited to multiplexed open microfluidic environmental biosensing and energy storage devices. Aspects of this invention introduce a one-step, mask-free process to create, pattern, and tune laser-induced graphene (LIG) with a ubiquitous CO2 laser or other laser. The laser parameters are adjusted to create LIG with different electrical conductivity, surface morphology, and surface wettability without the need for post chemical modification. This can be done with a single lasing. By optionally introducing a second (or third, fourth, or more) lasing(s), the LIG characteristics can be changed in just the same one step of using the laser scribing without other machines or sub-systems. One example is a second lasing with the same laser sub-system at low laser power, wherein the wettability of the LIG can be significantly altered. Such films presented unique superhydrophobicity owing to the combination of the micro/nanotextured structure and the removal of the hydrophilic oxygen-containing functional groups. The ability to tune the wettability of LIG while retaining high electrical conductivity and mechanical robustness allows rational design of LIG based on application.
AMORPHOUS METAL OXIDE SEMICONDUCTOR LAYER AND SEMICONDUCTOR DEVICE
Methods for producing the amorphous metal oxide semiconductor layer where amorphous metal oxide semiconductor layer is formed by use of a precursor composition containing a metal salt, a primary amide, and a water-based solution. The methodology for producing the amorphous metal oxide semiconductor layer includes applying the precursor composition onto a substrate to form a precursor film, and firing the film at a temperature of 150° C. or higher and lower than 300° C.
SEMICONDUCTOR DEVICE
Provided is a semiconductor device including: a semiconductor layer; a non-conductive layer that is in contact with at least a part of a side surface of the semiconductor layer directly or via another layer; and a Schottky electrode that is disposed on the semiconductor layer and the non-conductive layer, an end portion of the Schottky electrode being located above the non-conductive layer.
SPACE-FREE VERTICAL FIELD EFFECT TRANSISTOR INCLUDING ACTIVE LAYER HAVING VERTICALLY GROWN CRYSTAL GRAINS
A vertical field effect transistor according to an embodiment of the present invention does not require a spacer and, accordingly, remarkably alleviates the problem that electric charge is scattered at an interface, thereby having excellent electrical characteristics. The vertical field effect transistor includes a substrate, a source electrode positioned on the substrate, an active layer positioned on the source electrode and having vertically grown crystal grains, a drain electrode positioned on the active layer to be spaced by the active layer away from the source electrode, a gate insulating layer positioned on a lateral surface of the active layer, and a gate electrode positioned on the gate insulating layer.