A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

A method for manufacturing a semiconductor element of the present disclosure includes: a step of preparing a substrate; a first element forming step of forming a first semiconductor layer in a first region on a surface of the substrate; a first element separating step of separating the first semiconductor layer from the substrate; and a second element forming step of forming a second semiconductor layer in a second region on the surface of the substrate from which the first semiconductor layer is separated. Additionally, in the method for manufacturing a semiconductor element of the present disclosure, at least a portion of the second region overlaps the first region.

A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

Embodiments of the present disclosure generally relate to an integrated substrate processing system for cleaning a substrate surface and subsequently performing an epitaxial deposition process thereon. A processing system includes a film formation chamber, a transfer chamber coupled to the film formation chamber, and an oxide removal chamber coupled to the transfer chamber, the oxide removal chamber having a substrate support. The processing system includes a controller configured to introduce a process gas mixture into the oxide removal chamber, the process gas mixture including a fluorine-containing gas and a vapor including at least one of water, an alcohol, an organic acid, or combinations thereof. The controller is configured to expose a substrate positioned on the substrate support to the process gas mixture, thereby removing an oxide film from the substrate.

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

A group-III-nitride structure and a manufacturing method thereof are provided. In the manufacturing method, one or more grooves are formed by etching a first group-III-nitride epitaxial layer with a patterned first mask layer as a mask; then a second mask layer is formed at least on one or more bottom walls of the one or more grooves, and a first epitaxial growth is performed on the first group-III-nitride epitaxial layer to laterally grow and form a second group-III-nitride epitaxial layer with the second mask layer as a mask, where the one or more grooves are filled with the second group III-nitride epitaxial layer; a second epitaxial growth is then performed on the second group-III-nitride epitaxial layer to grow and form a third group-III-nitride epitaxial layer on the second group-III-nitride epitaxial layer and the patterned first mask layer.