A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

Semiconductor nanofibers are produced at room temperature in a pressure vessel. A semiconductor wafer and metal catalyst are introduced into the pressure vessel. The pressure vessel is filled with a background gas. A nanofiber growth element is introduced into the pressure vessel. For example, the semiconductor may be ablated by a laser. The semiconductor is retained in the pressure vessel for a prolonged period of time until nanofiber growth appears.

Provided herein are methods of performing liquid phase epitaxy (LPE) of III-V compounds and alloys at low pressures using pulsed nitrogen plasma to form an epitaxial layer e.g. on a substrate. The pulse sequence of plasma (with on and off time scales) enables LPE but avoids crust formation on top of molten metal. The concentration of nitrogen inside the molten metal is controlled to limit spontaneous nucleation.

A method for depositing III-V alloys on substrates and compositions therefrom. A first layer comprises a Group III element. A second layer comprises a silica. A substrate has a surface. The second layer is deposited onto a first layer. The depositing is performed by a sol-gel method. The second layer is exposed to a precursor that comprises a Group V element. At least one of the precursor or the Group V element diffuse through the silica. The first layer is transformed into a solid layer comprising a III-V alloy, wherein at least a portion of the first layer to a liquid. The silica retains the liquified first layer, enabling at least one of the precursor or the Group V element to diffuse into the liquid, resulting in the forming of the III-V alloy.

First, in a first step S101, a semiconductor layer composed of a p type Group III-V compound semiconductor is prepared. The semiconductor layer may be composed of a Group III-V compound semiconductor crystal. Next, in a second step S102, gold is grown on a surface of the above semiconductor layer according to an electroless plating method to form fine gold particles. In this step, for example, an electroless plating solution of gold is brought into contact with a surface of the semiconductor layer such as by immersing the semiconductor layer in the electroless gold plating solution. In addition, in this plating treatment, the liquid temperature of the electroless gold plating solution may be room temperature (about 20° C. to 30° C.).

A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

According to one embodiment, a crystal growth method includes forming a first member at at least a part of a bottom portion of a hole in a structure body. The hole includes the bottom portion and a side portion. The first member includes a first element. The first element is not adhered to at least a part of the side portion in the forming the first member. The crystal growth method includes growing a crystal member inside the hole by supplying a source material to the hole after the forming the first member. The source material includes a second element. The crystal member includes the second element.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of bit line contacts and a plurality of capacitor contacts disposed over the plurality of first regions and second regions; a landing pad disposed over one of the plurality of capacitor contacts, the landing pad comprising a protruding portion of a capacitor plug and a first spacer disposed on a sidewall of the protruding portion; a conductive plug disposed over the landing pad; and a plurality of bit lines disposed over the plurality of bit line contacts; and a capacitor structure disposed over the conductive plug. The capacitor plug includes a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.

Provided herein are methods of performing liquid phase epitaxy (LPE) of III-V compounds and alloys at low pressures using pulsed nitrogen plasma to form an epitaxial layer e.g. on a substrate. The pulse sequence of plasma (with on and off time scales) enables LPE but avoids crust formation on top of molten metal. The concentration of nitrogen inside the molten metal is controlled to limit spontaneous nucleation.

The present application discloses a semiconductor device with nanowire plugs and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of capacitor contacts positioned over the second regions, at least one of the capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the first regions and a plurality of bit lines positioned over the bit line contacts; a plurality of capacitor plugs disposed over the capacitor contacts, wherein at least one of the plurality of capacitor plugs includes a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and a plurality of capacitor structures disposed respectively over the capacitor plugs.