H01L21/2252

Ultrawide bandgap semiconductor devices including magnesium germanium oxides
11462400 · 2022-10-04 · ·

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the MgxGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Photolithography of atomic layer resist

In a method of atomic precision advanced manufacturing (APAM), an atomic or molecular resist layer on a substrate surface is selectively depassivated by locally exciting the substrate surface with an optical beam effective to eject adsorbed atoms or molecules from the substrate surface. The substrate surface is further processed by exposing it to a precursor gas, decomposing the precursor gas to release a dopant, and incorporating the dopant into the substrate surface.

Ultrawide bandgap semiconductor devices including magnesium germanium oxides
11456361 · 2022-09-27 · ·

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Semiconductor device, method of manufacturing the same, and electronic device including the device

A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

Vertically stacked transistors in a pin

An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

A METHOD FOR SELECTIVE INCORPORATION OF DOPANT ATOMS IN A SEMICONDUCTIVE SURFACE

The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic sites on the surface portion; dosing, at a temperature below 100 K, the surface portion using a gas with molecules comprising the dopant atom and hydrogen atoms in a manner such that, a portion of the molecules bonds to the surface portion; and incorporating one or more dopant atoms in a respective lithographic site by transferring an amount of energy to the dopant atoms. The number of dopant atoms incorporated in a lithographic site is deterministic and related to the size of the lithographic site.

Selective low temperature epitaxial deposition process

A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.

Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

Method and apparatus for depositing a monolayer on a three dimensional structure

In one embodiment, a processing apparatus may include a plasma chamber configured to generate a plasma; a process chamber adjacent the plasma chamber and configured to house a substrate that defines a substrate plane; an extraction system adjacent the plasma chamber and configured to direct an ion beam from the plasma to the substrate, the ion beam forming a non-zero angle with respect to a perpendicular to the substrate plane; and a molecular chamber adjacent the process chamber, isolated from the plasma chamber and configured to deliver a molecular beam to the substrate, wherein the ion beam and molecular beam are alternately delivered to the substrate to form a monolayer comprising species from the ion beam and molecular beam.

Method of fabricating image sensor

A method of fabricating an image sensor is provided. The method includes comprises forming a deep trench in a semiconductor substrate, performing a first plasma doping process to form a first impurity region a portion of in the semiconductor substrate adjacent to inner sidewalls and a bottom surface of the deep trench, the first impurity region being doped with first impurities of a first conductivity type, and performing an annealing process to diffuse the first impurities from the first impurity region into the semiconductor substrate to form a photoelectric conversion part.