Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. Also disclosed is single crystal Mg.sub.xGe.sub.1-xO.sub.2-x, with x having a value of 0?x<1. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a dopant chosen from Ga, Al, Li.sup.+, N.sup.3+. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a p-type conductivity.

Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

Various forms of Mg.sub.xGe.sub.1?xO.sub.2?x are disclosed, where an epitaxial layer comprises single crystal Mg.sub.xGe.sub.1?xO.sub.2?x, with x having a value of 0?x<1, wherein the single crystal Mg.sub.xGe.sub.1?xO.sub.2?x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal Mg.sub.xGe.sub.1?xO.sub.2?x is grown. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1?xO.sub.2?x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

A diffusion agent composition that can be evenly applied onto the whole area of an inner surface of the fine voids, whereby boron can be well and uniformly diffused into the semiconductor substrate even by heating at a low temperature, and a method for manufacturing a semiconductor substrate using the diffusion agent composition. In a diffusion agent composition including an impurity diffusion component, the impurity diffusion component, which can be applied onto a surface of a semiconductor substrate to form a diffusion layer, and which is a boron compound including a nitrogen atom, is used.

A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.

An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided.

There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar with each other, and the respective second source/drain layers of the first device and the second device are stressed differently.