A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

A p+ or n+ type doping process for semiconductors, allows to implement a semiconductor with a highly doped surface layer, and it comprises the steps of: providing a substrate made of semiconductor material; depositing on a surface of 5 the substrate made of semiconductor material a thin source layer made of dopant material acting as dopant source; depositing on said source layer an additional protective surface layer made of semiconductor material; inducing liquefaction of the surface layer at least until the source layer; and cooling down the substrate surface so as to obtain the diffusion of the dopant material.

Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.

Method for making a strained silicon structure, wherein a silicon germanium layer is formed on the silicon layer, followed by another layer with a lower concentration of germanium before selective amorphisation of the silicon and silicon germanium layer relative to this other layer before the assembly is recrystallised so as to strain the silicon semiconducting layer.

An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are formed, and in lower parts of the Si pillars, a second load P-channel, a second driver N-channel, and a second selection N-channel are formed. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the second load P-channel and the second driver N-channel. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the first load P-channel and the first driver N-channel. Gates surrounding the first and second selection N-channels are connected to a word-line terminal.

A method of defect reduction for a SiC layer includes activating dopants disposed in the SiC layer, depositing a carbon-rich layer on the SiC layer after activating the dopants, tempering the carbon-rich layer so as to form graphite on the SiC layer, and diffusing carbon from the graphite into the SiC layer. Carbon diffused from the graphite fills carbon vacancies in the SiC layer.

A gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.