A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

A semiconductor device includes a semiconductor substrate, an isolation structure, a gate structure, and a source/drain feature. The semiconductor substrate includes a semiconductor fin, wherein the semiconductor fin comprises a silicon germanium portion. The isolation structure is at a sidewall of a bottom portion of the silicon germanium portion. A top portion of the silicon germanium portion is higher than a top surface of the isolation structure, and an atomic concentration of germanium in the top portion of the silicon germanium portion is greater than an atomic concentration of germanium in the bottom portion of the silicon germanium portion. The gate structure is over a first portion of the silicon germanium portion of the semiconductor fin. The source/drain feature is over a second portion of the silicon germanium portion of the semiconductor fin.

A method for manufacturing a semiconductor device is provided. The method includes depositing a germanium layer over a silicon substrate; forming an oxide capping layer over the germanium layer; after forming the oxide capping layer, annealing the germanium layer to diffuse germanium atoms of the germanium layer into the silicon substrate, such that a portion of the silicon substrate is turned into a silicon germanium layer; and forming a gate structure over the silicon germanium layer.

A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

The invention provides a bifacial photovoltaic cell comprising: a semiconductor substrate, the substrate comprising an n+ layer on a first surface, and a p+ layer on a second surface. The n+ layer comprises an n-dopant and the p+ layer comprises a p-dopant. The cell further comprises a passivating and/or antireflective coating on the doped first and second surfaces. The cell is characterized in that the second surface of the semiconductor substrate has an area substantially devoid of the p-dopant on an edge of the second surface having a width in the range of 0.1-0.5 mm; wherein the area is formed by etching the semiconductor substrate.

A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.