The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices integrated with an ion-sensitive field-effect transistor (ISFET) and methods of forming the same. The semiconductor device may include a substrate, a reference gate structure disposed above the substrate, a floating gate structure disposed above the substrate and adjacent to the reference gate structure, where the reference gate structure is electrically coupled to the floating gate structure, and a dielectric layer disposed between the reference gate structure and the floating gate structure.

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

A semiconductor device includes: a first transistor that includes a first gate stack; a second transistor that includes a second gate stack having a narrower width than the first gate stack; and a dummy gate stack disposed around the first gate stack and the second gate stack, wherein the dummy gate stack includes an oxygen sink layer for capturing oxygen atoms that are diffused from an exterior into the first gate stack and the second gate stack.

A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming a gate electrode layer across the semiconductor fin, forming a first halogen-containing metal cap layer on the gate electrode layer, forming a contact structure on the source/drain structure and connected to the source/drain structure, and forming a second halogen-containing metal cap layer on the contact structure. The first halogen-containing metal cap layer and the second halogen-containing metal cap layer include different halogens.

A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.

An electronic device includes, a semiconductor layer, a source region and a drain region provided with the semiconductor layer to be interposed therebetween, a gate insulation film on the semiconductor layer between the source region and the drain region, and a gate of a graphene on the gate insulation film. The gate insulation film induces doping of charges in the graphene.

The instant disclosure discloses a method comprises receiving a substrate having a first region and a second region defined thereon and an insulating structure formed there-between; forming, extending across the first region and the second region, a gate stack including a dielectric layer and a gate ploy layer formed thereon; forming a first well mask covering the second region while defining a first opening that projectively overlaps the first region to partially exposes the gate ploy layer; performing a first doping process, through the first opening and the gate stack, to form a first well in the substrate beneath the first opening; and performing a second doping process through the first opening to form a first gate conductor in the gate ploy layer.