A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

A substrate fixing device includes a baseplate, an electrostatic attraction member, and an electrode pin. The baseplate includes a metallic member in which a through hole is famed. The electrostatic attraction member is over a surface of the baseplate and includes an attraction electrode. The electrode pin is inserted through the through hole to be connected to the attraction electrode. A recess communicating with the through hole is formed in the surface of the metallic member with the through hole being within the recess in a plan view from a direction perpendicular to the surface of the metallic member.

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1<Lg2; forming top spacers over the gates; and forming top source/drains over the top spacers. A VFET is also provided.

Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.