A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.

The disclosure is related to a display panel having a touch function and manufacture thereof, and the composite electrode thereof. The display panel comprises a composite electrode. The composite electrode comprises a metal electrode and a metal oxide layer formed on the surface of the metal electrode. Through the above configuration, the dense and insulated metal oxide layer is formed on the surface of the metal electrode of the composite electrode to prevent the composite electrode from forming a short-circuit with the peripheral circuits. Thus the yield for the display panel with a touch function is increased and the cost is reduced.

A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.

Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.

A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.

A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.