A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.

A method of manufacturing a TFT substrate and a manufacturing apparatus of a TFT substrate are provided. The method of manufacturing a TFT substrate comprises: forming active switches on a substrate; forming transparent electrode layer on the active switches; and forming a pixel layer on the transparent electrode layer. The step of forming the active switches on the substrate comprises: forming a metal layer on the substrate; bombarding the metal layer with hydrogen ions; and forming a protection layer on the metal layer.

A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.

A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.