A technique capable of controlling in-plane uniformity of a film formed on a substrate includes a step of forming a film on a substrate by performing a predetermined number of cycles in which a step of supplying a metal-containing gas to the substrate and a step of supplying a reducing gas containing an element that becomes a solid by itself to the substrate are performed in a time-division manner. The reducing gas has a property of changing a deposition rate of the film from an increasing rate to a decreasing rate in accordance with the exposure amount of the reducing gas with respect to the substrate. In the step of supplying the reducing gas, the exposure amount of the reducing gas with respect to the substrate is adjusted in accordance with the property of the reducing gas.

Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

A capacitor structure and a method for constructing the structure are described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.

Provided are methods for growing large-size, uniform graphene layers on planarized substrates using Chemical Vapor Deposition (CVD) at atmospheric pressure; graphene produced according to these methods may have a single layer content exceeding 95%. Field effect transistors fabricated by the inventive process have room temperature hole mobilities that are a factor of 2-5 larger than those measured for samples grown on commercially-available copper foil substrates.

There is provided a method of processing each of a plurality of substrates comprising: obtaining a first correction factor based on a first flow rate set value of a mass flow controller and a first measurement value of a mass flow meter; adjusting the first flow rate set value of the mass flow controller with the first correction factor so that the flow rate of the vaporized raw material becomes equal to a target value to process the substrate; obtaining a second correction factor based on a second flow rate set value of the mass flow controller and a second measurement value of the mass flow meter; and adjusting the second flow rate set value of the mass flow controller with the second correction factor so that the flow rate of the vaporized raw material becomes equal to the target value to process the substrate.

Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for forming substantially void-free and seam-free tungsten features in a semiconductor device manufacturing scheme. In one embodiment, a substrate processing system features a processing chamber and a gas delivery system fluidly coupled to the processing chamber. The gas delivery system includes a first radical generator for use in a differential inhibition treatment process and a second radical generator for use in a chamber clean process. The processing system is configured to periodically condition the first radial generator by forming a plasma of a relatively low amount of a halogen-based gas.

In a raw material gas supply apparatus, a control unit obtains an offset value of (m3(m1+m2)), m1, m2 and m3 being respective measurement values of first and second mass controllers, and a mass flow meter, by supplying a carrier gas and a dilution gas in a state where the carrier gas flows through a bypass channel. Further, the control unit obtains an actual measurement value of a flow rate of the raw material by subtracting the offset value from (m3(m1+m2)) obtained by supplying the carrier gas and dilution gas in a state where the carrier gas flows through the inside of a raw material container and calculating a difference between a target value of the flow rate of the raw material and the actual measurement value, and adjusts a set value of the first mass flow controller such that the flow rate of the raw material becomes.

There is provided a technique that includes: (A) forming a first layer containing a Group element on a surface of a substrate by supplying a gas containing the Group 15 element to the substrate; and (B) forming a film containing molybdenum on the first layer by performing: (a) supplying a gas containing molybdenum to the substrate; and (b) supplying a reducing gas to the substrate, wherein (a) and (b) are performed a predetermined number of times in (B) in an atmosphere capable of suppressing a decomposition of the first layer.

Provided is a method for packing a semiconductor, and more particularly, to a method for packaging a semiconductor, which packages the semiconductor device in a wafer level packaging manner. The method for packaging the semiconductor includes: preparing a wafer including a plurality of semiconductor devices; and forming a conductive pattern layer electrically connected to the plurality of semiconductor devices by using a mask member that is provided separately from the wafer.

A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.