The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×10.sup.14 cm.sup.−2 or more and 5×10.sup.15 cm.sup.−2 or less.

A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber.

The invention provides a raw material for chemical deposition having properties required for a CVD compound, that is, which has a high vapor pressure, can be formed into a film at low temperatures (about 250° C. or less), and also has moderate thermal stability. The invention relates to a raw material for chemical deposition, for producing a ruthenium thin film or a ruthenium compound thin film by a chemical deposition method, the raw material for chemical deposition including an organoruthenium compound represented by the following formula, in which a cyclohexadienyl group or a derivative thereof and a pentadienyl group or a derivative thereof are coordinated to ruthenium:

##STR00001## wherein the substituents R.sub.1 to R.sub.12 are each independently a hydrogen atom, a linear or cyclic hydrocarbon, an amine, an imine, an ether, a ketone, or an ester, and the substituents R.sub.1 to R.sub.12 each have 6 or less carbon atoms.

A method of processing each of a plurality of substrates comprises: obtaining a first correction factor based on a first flow rate set value of a mass flow controller and a first measurement value of a mass flow meter; adjusting the first flow rate set value of the mass flow controller with the first correction factor so that the flow rate of the vaporized raw material becomes equal to a target value to process the substrate; obtaining a second correction factor based on a second flow rate set value of the mass flow controller and a second measurement value of the mass flow meter; and adjusting the second flow rate set value of the mass flow controller with the second correction factor so that the flow rate of the vaporized raw material becomes equal to the target value to process the substrate.

An array substrate, a manufacturing method thereof and a display device are disclosed. Patterns comprising a gate, a gate insulating layer and a polysilicon active layer are formed on a base substrate by single patterning process. A passivation layer is formed on the substrate surface formed with the patterns, and patterns of a first via and a second via are formed on a surface of the passivation layer by single patterning process. Patterns of a source, a drain and a pixel electrode are formed on the substrate surface formed with the patterns by single patterning process. The source is electrically connected with the polysilicon active layer through the first via, and the drain is electrically connected with the polysilicon active layer through the second via. A pattern of pixel defining layer is formed on the substrate surface formed with the patterns by single patterning process.

The present disclosure provides a thin film transistor, including: an active layer, a source and a drain electrically coupled with the active layer, and a plurality of doped layers located between the source and the active layer and between the drain and the active layer, a resistance of one of the plurality of doped layers farthest away from the active layer is smaller than that of any other doped layer. The disclosure further provides a gate driving circuit, a display substrate and a display device. With the present disclosure, current loss of a current passing through the doped layers of the thin film transistor is reduced, on-state current of the thin film transistor is improved and a situation that output signals of the thin film transistor are insufficient is avoided.

There is provided a technique capable of forming a low resistance film. The technique includes sequentially repeating: a first step including a first process of supplying a reducing gas containing silicon and hydrogen and not containing halogen, in parallel with supply of a metal-containing gas, to a substrate in a process chamber; a second step including: a second process of stopping the supply of the metal-containing gas, and maintaining the supply of the reducing gas; and a third process of supplying an inert gas into the process chamber with the supply of the reducing gas stopped, and maintaining a pressure in the third process equal to a pressure in the second process or adjusting the pressure in the third process to a pressure different from the pressure in the second process; and a third step of supplying a nitrogen-containing gas to the substrate.

A deposition mask group includes a first deposition mask having two or more first through holes arranged along two different directions, a second deposition mask having two or more second through holes arranged along two different directions and a third deposition mask having two or more third through holes. The first through hole and the second through hole or the third through hole partly overlap when the first deposition mask, the second deposition mask and the third deposition mask are overlapped.