Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.

Disclosed are an array substrate of a thin-film transistor liquid crystal display device and a method for manufacturing the same. The array substrate includes a plurality of data lines, a plurality of dummy data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of groups of pixel units. Each group of pixel units includes an odd-numbered column of first thin film transistors and an even-numbered column of second thin film transistors. First ends and second ends of the dummy data lines are connected respectively to two common voltage electrode lines, which are arranged on the substrate in a transverse direction. The method includes steps of: forming a plurality of gate lines and two common voltage electrode lines; forming a source, a drain, and a plurality of data lines; and forming a plurality of pixel electrodes and a plurality of dummy data lines. A light shielding electrode line provided has good voltage driving uniformity.

The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.

A method for fabricating a capacitor structure is described. The method for metal insulator metal capacitor in an integrated circuit device includes forming a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is formed in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is formed over the extended top face of the bottom capacitor plate. A top capacitor plate is formed in a top, remainder portion of the trench on top of the high-k dielectric layer.

Provided is a method for depositing a metal thin film by atomic layer deposition (ALD) using an organometallic complex as a source material and without using radical species such as plasma and ozone, which have a possibility of deactivation. The method is an atomic layer deposition (ALD) method for metal thin films which includes: a process of supplying an organometallic complex having an aromatic anionic ligand and/or an alkyl ligand into a reaction chamber in which a substrate is installed; and a process of supplying a mixture gas containing a nucleophilic gas and an electrophilic gas into the reaction chamber, the ALD method substantially not using either one of a gas in a plasma or radical state and a gas containing oxygen atoms.

Apparatus and methods to process one or more wafers are described. A spatial deposition tool comprises a plurality of substrate support surfaces on a substrate support assembly and a plurality of spatially separated and isolated processing stations. The spatially separated isolated processing stations have independently controlled temperature, processing gas types, and gas flows. In some embodiments, the processing gases on one or multiple processing stations are activated using plasma sources. The operation of the spatial tool comprises rotating the substrate assembly in a first direction, and rotating the substrate assembly in a second direction, and repeating the rotations in the first direction and the second direction until a predetermined thickness is deposited on the substrate surface(s).