The uniformity of electroplating a metal (e.g., copper) on a semiconductor wafer is improved by using an electroplating apparatus having a flow-shaping element positioned in the proximity of the semiconductor wafer, wherein the flow-shaping element is made of a resistive material and has two types of non-communicating channels made through the resistive material, such that the electrolyte is transported towards the substrate through both types of channels. The first type of channels is not perpendicular to the plane defined by a plating face of the substrate. The second type of channels is perpendicular to the plane defined by the plating face of the substrate. The channels of the first and second type are substantially spatially segregated. In one embodiment a plurality of channels of the first type are located in the central portion of the flow-shaping element and are surrounded by a plurality of channels of the second type.

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

A substrate holder for vertical galvanic metal deposition on a substrate, comprising a first substrate holder part and a second substrate holder part, wherein both said parts comprise an inner metal comprising part and an outer non-metallic part in which the substrate holder further comprises a hanging element in each substrate holder part, a first sealing element in each substrate holder part, a second sealing element between the inner metal comprising part and the outer non-metallic part of the substrate holder, a fastening system for detachably fastening both substrate holder parts to each other, a first contact element in each substrate holder part for forwarding current from an outer source through the hanging element to the at least second contact element, and a second contact element in each substrate holder part for forwarding current from the at least first contact element to the substrate to be treated.

Systems and methods of in-situ calibration of semiconductor material layer deposition and Removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.

Provided are an apparatus for and a method of processing a substrate. The substrate processing apparatus includes a substrate processing unit to process a substrate using a processing solution containing a mixture of first and second sources; a source supplying part to supply the first and second sources to the substrate processing unit; at least one analyzer to measure a concentration of the second source in the processing solution or a pH value of the processing solution and adjust a measurement reference value of the second source in the processing solution using a standard solution, in which the first and second sources are mixed to have a predetermined concentration or pH value; and a standard solution supplying part to prepare the standard solution using the first and second sources to be supplied from the source supplying part and to supply the standard solution to the at least one analyzer.

A photosensitive resin composition comprises: a resin having a phenolic hydroxyl group; a photosensitive acid generator; a compound having at least one selected from the group consisting of an aromatic ring, a heterocycle and an alicycle, and at least one selected from the group consisting of a methylol group and an alkoxyalkyl group; and an aliphatic compound having two or more functional groups, the functional groups being at least one functional group selected from the group consisting of an acryloyloxy group, a methacryloyloxy group, a glycidyloxy group, an oxetanyl alkyl ether group, a vinyl ether group and a hydroxyl group, wherein the photosensitive acid generator is a sulfonium salt containing an anion having at least one skeleton selected from the group consisting of a tetraphenylborate skeleton, an alkylsulfonate skeleton having 1 to 20 carbon atoms, a phenylsulfonate skeleton and a 10-camphorsulfonate skeleton.

Electrical components may be packaged using system-in-package configurations or other component packages. Integrated circuit dies and other electrical components may be soldered or otherwise mounted on printed circuits. A layer of encapsulant may be used to encapsulate the integrated circuits. A shielding layer may be formed on the encapsulant layer to shield the integrate circuits. The shielding layer may include a sputtered metal seed layer and an electroplated layer of magnetic material. The electroplated layer may be a magnetic material that has a high permeability such as permalloy or mu metal to provide magnetic shielding for the integrated circuits. Integrated circuits may be mounted on one or both sides of the printed circuit. A temporary carrier and sealant may be used to hold the encapsulated integrated circuits during electroplating.

A non-uniform initial metal film is non-uniformly deplated to provide a more uniform metal film on a substrate. Electrochemical deplating may be performed by placing the substrate in a deplating bath formulated specifically for deplating, rather than for plating. The deplating bath may have a throwing power of 0.3 or less; or a bath conductivity of 1 mS/cm to 250 mS/cm. Reverse electrical current conducted through the deplating bath non-uniformly. electro-etches or deplates the metal film.

A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region and a process region, wherein the substrate support is configured to rotate the substrate; a solution container configured to hold an electroless deposition solution; a dispenser configured to provide a flow of the electroless deposition solution; a controller, the controller configured to direct the flow of the electroless deposition solution toward the edge exclusion region while the substrate is rotated, the flow being directed away from the process region, the electroless deposition solution plates metallic material over the conductive layer at the edge exclusion region, to produce an increased thickness of the metallic material that reduces electrical resistance.

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.