A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on the first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask retreating from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

A cleaning apparatus is provided. This cleaning apparatus includes an inlet, an outlet, a first conveyance path, a second conveyance path, a cleaning unit disposed on the first conveyance path and configured to clean the target object in a non-contacting manner, and a drying unit disposed on the first conveyance path and configured to dry the target object in a non-contacting manner. The first conveyance path and the second conveyance path are vertically arranged side by side. The second conveyance path is positioned above the first conveyance path and connected with the outlet at an end point. The second conveyance path functions as a stocker configured to temporarily store the target object.

Described herein is a composition for depositing copper on a semiconductor substrate, the composition including

(a) copper ions;
(b) an additive of formula S1

##STR00001##

(c) a complexing agent; and
(d) optionally a buffer or base capable of adjusting the pH to a pH of from 7 to 13;
where the variables are as defined herein; and
where the pH of the composition is from 7 to 13 and where the composition is free of any cyanide.

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

To partially or locally control a plating film thickness on a polygonal substrate. There is provided a regulation plate for adjusting a current between an anode and the polygonal substrate. This regulation plate includes a main body that has an edge forming a polygonal opening through which the current passes and an attachable/detachable shielding member to shield at least a part of the polygonal opening.

In manufacturing of a first electroformed component and a second electroformed component having portions fitted to each other into close contact, after the first electroformed component is formed, the first electroformed component is used as a portion of an electroforming mold to form the second electroformed component. Using the first electroformed component as a portion of the electroforming mold to form the second electroformed component, the shape of the first electroformed component is transferred to the second electroformed component. As a result, multiple types of components differing in shape may be accurately manufactured concurrently in a series of manufacturing steps.

A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. The method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

Structures and methods for direct bonding are disclosed. A bonded structure can include a first element and a second element. The first element can include a first non-conductive structure that has a non-conductive bonding surface, a cavity that extends at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature that has a first conductive material and a second conductive material over the first conductive material disposed in the cavity. A maximum grain size, in a linear lateral dimension, of the second conductive material can be smaller than 20% of the linear lateral dimension of the conductive feature. There can be less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.