A method of forming a composite crystalline nitride structure is provided. The method includes depositing a first crystalline nitride layer on a substrate, patterning the first crystalline nitride layer to form a patterned crystalline nitride layer having a top surface and that includes undulations, annealing the patterned crystalline nitride layer at a temperature between 300° C. to 850° C. to form an annealed patterned crystalline nitride layer, and depositing a second crystalline nitride layer on the annealed patterned crystalline nitride layer. The second crystalline nitride layer is lattice-matched to the underlying annealed patterned crystalline nitride layer to within 2%, thereby forming the composite crystalline nitride structure.

Devices for fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

Manufacturing a device may include inspecting a surface of an inspection target device. The inspecting may include forming a metal layer on a surface of the inspection target device on which a minute pattern is formed, directing a beam of light to be incident and normal to the surface of the inspection target device, determining a spectrum of light reflected from the surface of the inspection target device, and generating, via the spectrum, information associated with a structural characteristic of the minute pattern formed on the inspection target device. The inspection target device may be selectively incorporated into the manufactured device based on the generated information.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

A method for making EMI shielding layer of a package is disclosed to include the steps of: a) disposing a UV curable adhesive, which can be thermally released, on a surface of a package panel having solder pads to cover the solder pads; b) curing the UV curable adhesive; c) performing a singulating process to form the plurality of the packages disposed by the UV curable adhesive; d) forming an EMI shielding layer on the package; and e) thermally releasing the UV curable adhesive.

Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Provided is a wafer-level package with metal shielding structure and the manufacturing method for producing the same. The wafer-level package includes first conductive structures for securing a die unit to a substrate, and is featured by disposing one or more second conductive structures that are located at the front surface of the die unit and proximate to a side surface of the die unit. The second conductive structure does not electrically connected to the internal circuitry of the die unit. After the wafer is cut, a metal shielding layer is formed on the back surface and the side surfaces of the die unit. Afterwards, the die unit is mounted on the substrate to allow the second conductive structure to connect to the ground structure on the substrate and connect to the metal shielding layer. Thus, EMI shielding function is generated to efficiently suppress EMI and miniaturize the package.

A cleaning method according to one aspect of the present disclosure which cleans an electrostatic chuck includes exposing the electrostatic chuck to plasma and maintaining a relationship between a potential of the electrostatic chuck and a potential of the plasma such that electron current is introduced from the plasma toward the electrostatic chuck.