Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.

Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.

A semiconductor structure and a method for forming same are provided, the forming method including: providing a base including a plurality of adjacent device unit regions, an initial device gate structure spanning a plurality of device unit regions being formed on the base; etching a portion of the initial device gate structure in thickness at a junction between the adjacent device unit regions to form a top opening; forming a spacer layer on a side wall of the top opening; etching a remainder of the initial device gate structure exposed from the spacer layer, and forming a bottom opening exposed from the base within the remainder of the initial device gate structure, the remainder of the initial device gate structure being used as a device gate structure; and forming an isolation structure within the top opening and the bottom opening. The spacer layer is configured to adjust a width of the bottom opening, so that the width of the bottom opening is less than a width of the top opening. Therefore, the width of the top opening can be increased properly to enlarge a process window in which the top opening is formed, thereby better implementing isolation between the adjacent device unit regions and improving integrity of the device gate structure, further helping improve performance of a transistor.

A semiconductor structure and a method for forming same are provided, the forming method including: providing a base including a plurality of adjacent device unit regions, an initial device gate structure spanning a plurality of device unit regions being formed on the base; etching a portion of the initial device gate structure in thickness at a junction between the adjacent device unit regions to form a top opening; forming a spacer layer on a side wall of the top opening; etching a remainder of the initial device gate structure exposed from the spacer layer, and forming a bottom opening exposed from the base within the remainder of the initial device gate structure, the remainder of the initial device gate structure being used as a device gate structure; and forming an isolation structure within the top opening and the bottom opening. The spacer layer is configured to adjust a width of the bottom opening, so that the width of the bottom opening is less than a width of the top opening. Therefore, the width of the top opening can be increased properly to enlarge a process window in which the top opening is formed, thereby better implementing isolation between the adjacent device unit regions and improving integrity of the device gate structure, further helping improve performance of a transistor.

A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl.sub.2 and BCl.sub.3

A light emitting device includes a vertical stack of a light emitting diode and a field effect transistor that controls the light emitting diode. An isolation layer is present between the light emitting diode and the field effect transistor, and an electrically conductive path electrically shorts a node of the light emitting diode to a node of the field effect transistor. The field effect transistor may include an indium gallium zinc oxide (IGZO) channel and may be located over the isolation layer. Alternatively, the field effect transistor may be a high-electron-mobility transistor (HEMT) including an epitaxial semiconductor channel layer and the light emitting diode may be located over the HEMT.

Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by providing a substrate having a plurality of protruding tin oxide features (mandrels) residing on an exposed etch stop layer. Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrel (e.g., leaving at least 50%, such as at least 90% of initial height at the sidewall). Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning the etch stop layer and underlying layers.