A thin film transistor is disclosed. The thin-film transistor includes an active layer (3); a source electrode (1); and a drain electrode (2). The active layer includes an active pattern region (4), the active pattern region including a main body portion (5) and a plurality of protrusion portions (6) on both sides of the main body portion. The protrusion portions are connected to the main body portion.

The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

A semiconductor resist composition includes an organometallic compound represented by Chemical Formula 1 and a solvent: ##STR00001## wherein, in Chemical Formula I, R.sup.1 is an aliphatic hydrocarbon group, an aromatic hydrocarbon group, or an —alkylene-O-alkyl group, and R.sup.2 to R.sup.4 are each independently selected from —OR.sup.a and —OC(═O)R.sup.b, where R.sup.a is not hydrogen.

A semiconductor resist composition includes an organometallic compound represented by Chemical Formula 1 and a solvent: ##STR00001## wherein, in Chemical Formula I, R.sup.1 is an aliphatic hydrocarbon group, an aromatic hydrocarbon group, or an —alkylene-O-alkyl group, and R.sup.2 to R.sup.4 are each independently selected from —OR.sup.a and —OC(═O)R.sup.b, where R.sup.a is not hydrogen.

A method for etching an oxide semiconductor film includes: providing a substrate including a mask of a silicon-containing film on an oxide semiconductor film containing at least indium (In), gallium (Ga), and zinc (Zn); supplying a processing gas containing a bromine (Br)-containing gas or an iodine (I)-containing gas; and etching the oxide semiconductor film by plasma generated from the processing gas.

A method for etching an oxide semiconductor film includes: providing a substrate including a mask of a silicon-containing film on an oxide semiconductor film containing at least indium (In), gallium (Ga), and zinc (Zn); supplying a processing gas containing a bromine (Br)-containing gas or an iodine (I)-containing gas; and etching the oxide semiconductor film by plasma generated from the processing gas.

A display substrate, a manufacturing method thereof, and a display device. The manufacturing method of a display substrate includes: providing a substrate; and forming, on the substrate, a first thin film transistor including a first active layer and a second thin film transistor including a second active layer. The second active layer includes a central area and doped regions located at two sides of the central area, respectively. Forming a first thin film transistor including a first active layer and a second thin film transistor including a second active layer on the substrate includes forming the first active layer and the doped regions of the second active layer using a single mask.

The invention relates to the chemical etching of a semiconductor material, including: deposition at least one mask (PLP) on a first surface zone of a semiconductor material (SC); and chemically etching (S31) a second surface zone of the semiconductor material (SC) that is not covered by the mask (PLP). In particular, the aforementioned mask is produced in a material including polyphosphazene, which material protects the underlying semiconductor especially well.

The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.