H01L21/475

SRAM structure and method

Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

SRAM structure and method

Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

Metal plate for deposition mask, and deposition mask and manufacturing method therefor

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Metal plate for deposition mask, and deposition mask and manufacturing method therefor

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

APPARATUS FOR PROCESSING SUBSTRATE AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME

Provided is an apparatus for processing a substrate, the apparatus including: a processing chamber configured to provide a processing space; a fluid supply device configured to supply a supercritical fluid to the processing chamber; a fluid discharge device configured to discharge the supercritical fluid from the processing chamber; and a control device configured to control operations of the fluid supply device and the fluid discharge device, wherein the fluid supply device includes a first supply line connected to an upper portion of the processing chamber and a second supply line connected to a lower portion of the processing chamber, and the control device is configured to perform a plurality of first cycles in which the supercritical fluid is alternately supplied into the processing space through the first supply line and the second supply line to boost pressure in the processing space to a set pressure.

APPARATUS FOR PROCESSING SUBSTRATE AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME

Provided is an apparatus for processing a substrate, the apparatus including: a processing chamber configured to provide a processing space; a fluid supply device configured to supply a supercritical fluid to the processing chamber; a fluid discharge device configured to discharge the supercritical fluid from the processing chamber; and a control device configured to control operations of the fluid supply device and the fluid discharge device, wherein the fluid supply device includes a first supply line connected to an upper portion of the processing chamber and a second supply line connected to a lower portion of the processing chamber, and the control device is configured to perform a plurality of first cycles in which the supercritical fluid is alternately supplied into the processing space through the first supply line and the second supply line to boost pressure in the processing space to a set pressure.

REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGES

A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGES

A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

METAL PLATE FOR DEPOSITION MASK, AND DEPOSITION MASK AND MANUFACTURING METHOD THEREFOR

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

METAL PLATE FOR DEPOSITION MASK, AND DEPOSITION MASK AND MANUFACTURING METHOD THEREFOR

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.