A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.

A semiconductor package structure includes a semiconductor die, at least one wiring structure, a metal support, a passive element, a plurality of signal vias, and a plurality of thermal structures. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The metal support is used for supporting the semiconductor die. The passive element is electrically connected to the semiconductor die. The signal vias are electrically connecting the passive element and the semiconductor die. The thermal structures are connected to the passive element, and the thermal structures are disposed on a periphery of the at least one wiring structure.

A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite to the first surface, an encapsulant, and an antenna. The encapsulant is disposed on the first surface of the carrier. The antenna is disposed on the encapsulant. The antenna includes a seed layer and a conductive layer.

The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

A manufacturing method of a semiconductor device includes mounting a semiconductor element on a first electrode disposed on a first surface of a substrate; preparing a metal plate including a main body part and a projection part; mounting the metal plate on the first surface side of the substrate, by joining the projection part to a second electrode that is disposed on the first surface of the substrate; sealing the semiconductor element and the projection part with a sealing resin; and forming an electrode terminal made of a base end part that is connected to the second electrode and has a side surface that is covered by the sealing resin, and a tip end part that is integrally formed with the base end part and that projects from a front surface of the sealing resin, by etching the main body part excluding a portion overlapping with the projection part.

A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.