Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/70
Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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H01L21/71
Manufacture of specific parts of devices defined in group H01L21/70
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H01L21/76
Making of isolation regions between components
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H01L21/762
Dielectric regions; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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H01L21/76202
using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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H01L21/76205
in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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H01L21/7621
the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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H01L21/7621

METHOD FOR FORMING FLASH MEMORY
20250372440 · 2025-12-04 ·

A method for forming a flash memory is provided. The method includes forming a strip pattern, which includes an active region, a pad oxide layer, a protection layer, an etch stop layer, and a mask layer sequentially stacked on a semiconductor substrate. The sidewalls of the strip pattern are exposed from first trenches. The method also includes forming an isolation structure in the first trench, etching the mask layer of the strip pattern to form the second trench until the etch stop layer is exposed, performing an oxidation process on the active region, removing the etch stop layer, removing the protection layer, and forming a first gate electrode layer in the second trench.