Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/70
Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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H01L21/71
Manufacture of specific parts of devices defined in group H01L21/70
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H01L21/76
Making of isolation regions between components
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H01L21/762
Dielectric regions; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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H01L21/76224
using trench refilling with dielectric materials
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H01L21/76232
of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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H01L21/76235
trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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H01L21/76235

Method for fabricating semiconductor device with chelating agent
12341054 · 2025-06-24 · ·

The present application discloses a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes forming a first dielectric layer on a substrate; forming a feature opening to exposing the substrate; performing a pre-cleaning treatment including a pre-cleaning solution to the feature opening; performing a cleaning process to the feature opening; and forming a conductive feature in the feature opening. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor.