A method for manufacturing an SOI wafer by performing a sacrificial oxidation treatment and reducing a thickness of an SOI layer of the SOI wafer, in which: the SOI wafer on which the sacrificial oxidation treatment is performed has a film thickness distribution with a one-way sloping shape; a thermal oxidation in the sacrificial oxidation treatment is performed by combining a non-rotating oxidation and a rotating oxidation, using a vertical heat treatment furnace; whereby a thermal oxide film having an oxide film thickness distribution with a one-way sloping shape canceling the film thickness distribution with a one-way sloping shape of the SOI layer, is formed on a surface of the SOI layer; and by removing the formed thermal oxide film, an SOI wafer having an SOI layer whose film thickness distribution with a one-way sloping shape has been resolved is manufactured.

A hybrid substrate has an SOI structure having a good silicon active layer, without defects such as partial separation of the silicon active layer is obtained without trimming the outer periphery of the substrate. An SOI substrate is obtained by sequentially laminating a first silicon oxide film and a silicon active layer in this order on a silicon substrate. A terrace portion that does not have the silicon active layer is formed in the outer peripheral portion of the silicon substrate surface. A second silicon oxide film is formed on the silicon active layer surface of the SOI substrate The bonding surfaces of the SOI substrate and a supporting substrate that has a thermal expansion coefficient different from that of the SOI substrate is subjected to an activation treatment. The SOI substrate and the supporting substrate are bonded with the second silicon oxide film being interposed therebetween.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

According to one embodiment, a semiconductor device is provided with a first single crystal layer, a polycrystalline layer provided on an entire surface of the first single crystal layer, and a second single crystal layer bonded to the polycrystalline layer. The coefficient of thermal expansion of the polycrystalline layer is greater than the coefficient of thermal expansion of the second single crystal layer, and is smaller than the coefficient of thermal expansion of a compound semiconductor layer which can be provided on the second single crystal layer using an intervening a buffer layer.

The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.

A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.