An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

A highly thermal conductive substrate formed by bonding a device layer formed on a silicon on insulator (SOI) wafer and a buried oxide film to an insulator substrate having a thermal conductivity of 40 W/m.Math.K or more via a low-stress adhesive, wherein a thickness of the buried oxide film is 50 to 500 nm and a thickness of the adhesive is 0.1 to 10 μm.

The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.

A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

To provide a method for producing a composite wafer capable of reducing a spurious arising by reflection of an incident signal on a joint interface between a lithium tantalate film and a supporting substrate, in the composite wafer including a supporting substrate having a low coefficient of thermal expansion, and a lithium tantalate film having a high coefficient of thermal expansion stacked on the supporting substrate. The method for producing a composite wafer is a method for producing a composite wafer that produces a composite wafer by bonding a lithium tantalate wafer having a high coefficient of thermal expansion to a supporting wafer having a low coefficient of thermal expansion, wherein prior to bonding together, ions are implanted from a bonding surface of the lithium tantalate wafer and/or the supporting wafer, to disturb crystallinity near the respective bonding surfaces.

Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 μm or more. A sheet resistance of a group III-nitride-film-side main surface is 200 Ω/sq or less.

A method of transferring a device layer in a SOI wafer obtained by stacking a Si layer, an insulator layer, and the device layer to a transfer substrate, includes a step of temporarily bonding a surface on which the device layer is formed of the SOI wafer to a supporting substrate using an adhesive for temporary bonding, a step of removing the Si layer of the SOI wafer until the insulator layer is exposed and obtaining a thinned device wafer, a step of coating only the transfer substrate with an adhesive for transfer and then bonding the insulator layer in the thinned device wafer to the transfer substrate via the adhesive for transfer, a step of thermally curing the adhesive for transfer under a load at the same time as or after bonding, a step of peeling off the supporting substrate, and a step of removing the adhesive.