H01L21/76259

Wafer Production Method
20200185267 · 2020-06-11 ·

A method for producing a layer of solid material includes: providing a solid body having opposing first and second surfaces, the second surface being part of the layer of solid material; generating defects by means of multiphoton excitation caused by at least one laser beam penetrating into the solid body via the second surface and acting in an inner structure of the solid body to generate a detachment plane, the detachment plane including regions with different concentrations of defects; providing a polymer layer on the solid body; and subjecting the polymer layer to temperature conditions to generate mechanical stress in the solid body, including cooling of the polymer layer to a temperature below ambient temperature, the cooling taking place such that due to stresses a crack propagates in the solid body along the detachment plane and the layer of solid material separates from the solid body along the crack.

Method for manufacturing a semiconductor structure with temporary direct bonding using a porous layer

A method for manufacturing a semiconductor structure, including: direct bonding a substrate to be handled with a handle substrate via a bonding layer covering the handle substrate, to form a temporary structure capable of withstanding technological steps; disassembling the temporary structure at the bonding layer to separate the substrate to be handled from the handle substrate; and a prior depositing the bonding layer onto the handle substrate and/or onto the substrate to be handled, the bonding layer including a porous material including, an inorganic matrix and organic compounds connected or not to the matrix, and the disassembling is carried out by providing a thermal budget for disassembly to the intermediate structure, the providing resulting in a spontaneous disassembly of the temporary structure occurring at the bonding layer.

Combined wafer production method with laser treatment and temperature-induced stresses

A method for the production of layers of solid material is contemplated. The method may include the steps of providing a solid body for the separation of at least one layer of solid material, generating defects by means of at least one radiation source, in particular a laser, in the inner structure of the solid body in order to determine a detachment plane along which the layer of solid material is separated from the solid body, and applying heat to a polymer layer disposed on the solid body in order to generate, in particular mechanically, stresses in the solid body, due to the stresses a crack propagating in the solid body along the detachment plane, which crack separates the layer of solid material from the solid body.

Methods of forming strained-semiconductor-on-insulator device structures

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Combined wafer production method with laser treatment and temperature-induced stresses
20190237359 · 2019-08-01 ·

A method for the production of layers of solid material is contemplated. The method may include the steps of providing a solid body for the separation of at least one layer of solid material, generating defects by means of at least one radiation source, in particular a laser, in the inner structure of the solid body in order to determine a detachment plane along which the layer of solid material is separated from the solid body, and applying heat to a polymer layer disposed on the solid body in order to generate, in particular mechanically, stresses in the solid body, due to the stresses a crack propagating in the solid body along the detachment plane, which crack separates the layer of solid material from the solid body.

Combined wafer production method with laser treatment and temperature-induced stresses

A method for the production of layers of solid material is contemplated. The method may include the steps of providing a solid body for the separation of at least one layer of solid material, generating defects by means of at least one radiation source, in particular a laser, in the inner structure of the solid body in order to determine a detachment plane along which the layer of solid material is separated from the solid body, and applying heat to a polymer layer disposed on the solid body in order to generate, in particular mechanically, stresses in the solid body, due to the stresses a crack propagating in the solid body along the detachment plane, which crack separates the layer of solid material from the solid body.

Method for forming semiconductor-on-insulator (SOI) substrate by cleaving a multilayer structure along voids to separate a substrate

A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

Methods for processing a 3D semiconductor device
10297586 · 2019-05-21 · ·

A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.

SEMICONDUCTOR DEVICE AND STRUCTURE WITH THERMAL ISOLATION
20190057959 · 2019-02-21 · ·

A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m.Math.K thermal conductivity.

METHOD FOR FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE
20240282775 · 2024-08-22 ·

A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.