Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

A structure includes an active device over an area of a substrate, and a heat spreading isolation structure adjacent the active device. The isolation structure includes a dielectric layer above a heat-conducting layer. The heat-conducting layer may include polycrystalline graphite. The heat-conducting layer provides a heat sink, which provides a high thermal conductivity path for heat with low electrical conductivity. The heat-conducting layer may extend into the substrate. The substrate may include an SOI substrate in which case the heat-conducting layer may extend through the buried insulator thereof.

In some embodiments, the present disclosure relates to a method that includes forming a shallow trench isolation (STI) structure that extends into a substrate. A masking layer is formed over the substrate and includes an opening overlying the STI structure. A first removal process removes portions of the STI structure underlying the opening of the STI structure. A second removal process laterally removes portions of the substrate below the STI structure. A third removal process removes portions of the substrate that directly underlie the opening of the masking layer. An insulator liner layer is formed within inner surfaces of the substrate as defined by the first, second, and third removal processes. Further, a fourth removal process removes portions of the insulator liner layer covering a lower surface of the substrate. A semiconductor material is then formed over the SOI substrate and on the insulator liner layer.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

A capacitor includes an electrode implemented in an electrode well of a substrate. The electrode well has a net N-type dopant concentration. The capacitor includes an electrode implemented in a conductive structure located above the substrate. The electrodes are separated by a dielectric layer located between the electrodes. A first tub region having a net P-type conductivity dopant concentration is located below and laterally surrounds the electrode well and a second tub region having a net N-type conductivity dopant concentration is located below and laterally surrounds the first tub region and the electrode well.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.