Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

In forming a semiconductor structure, a two-step breakthrough etching method is employed in which a glue layer and dielectric liner are broken-through sequentially in order to successfully gain device performance and avoid drain or gate metal damage.

The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.

Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.

The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

A blocking material is selectively deposited on a bottom surface of a back end of line (BEOL) conductive structure such that a barrier layer is selectively deposited on sidewalls of the BEOL conductive structure but not the bottom surface. The blocking material is etched such that copper from a conductive structure underneath is exposed, and a ruthenium layer is deposited on the barrier layer but less ruthenium is deposited on the exposed copper. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is substantially absent from the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium layer reduces surface roughness within the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance.

Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.