The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

The present disclosure provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die, forming a first mask layer on the second die, forming a first opening along the first mask layer and the second die, and extending to the first die, forming isolation layers on sidewalls of the first opening, forming protection layers covering upper portions of the isolation layers, and forming a conductive filler layer in the first opening.

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

A system and method for reducing thermal transfer in a dual ampoule system. The dual ampoule system includes a first ampoule, a second ampoule, and a planar heat shield. The planar heat shield is positioned between the first ampoule and the second ampoule, where the planar heat shield is configured to resist thermal transfer between the first ampoule and the second ampoule.

Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.

An interconnect structure comprising a low via resistance via structure is disclosed. The via structure comprises a barrier layer on sidewalls and at bottom of the via structure. The interconnect structure also includes a first metal layer. The interconnect structure further includes a second metal layer between the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials.

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second conductive feature disposed in the first dielectric layer, an etch stop layer disposed on the first dielectric layer, a second dielectric layer disposed on the etch stop layer, and a third conductive feature disposed in the second dielectric layer and the etch stop layer. The third conductive feature includes a first conductive layer, which includes a two-dimensional material. The structure further includes a fourth conductive feature disposed in the second dielectric layer and the etch stop layer. The third conductive feature and the fourth conductive feature include different number of layers.

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.