A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.

Various embodiments generally relate to a method for forming a graphene barrier layer for a semiconductor device, and more particularly, to a method of forming a barrier thin film including a graphene layer capable of reducing the contact resistance of a metal interconnect. A method for forming a graphene barrier layer according to an embodiment includes: loading a substrate, which has a titanium-containing layer formed thereon, in a chamber of a substrate processing system, the chamber having a processing space formed therein; inducing nucleation on the titanium-containing layer by supplying a first reactant gas including a unsaturated hydrocarbon into the chamber; and forming a graphene layer on the titanium-containing layer by supplying a second reactant gas including a saturated hydrocarbon into the chamber.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-κ dielectric is formed on the conformal layer such that the low-κ dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-κ dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, hydroxyl, aldehyde, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

Described are microelectronic devices and methods for forming interconnections in microelectronic devices. Embodiments of microelectronic devices include tantalum-containing barrier films comprising an alloy of tantalum and a metal dopant selected from the group consisting of ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), and iridium (Ir).

A method of making a semiconductor component includes forming an interconnect in a dielectric layer such that an uppermost surface of the interconnect is substantially coplanar with an uppermost surface of the dielectric layer. The method further includes recessing the dielectric layer such that the uppermost surface of the dielectric layer is lower than the uppermost surface of the interconnect. The method further includes forming spacers in direct contact with the uppermost surface of the recessed dielectric layer such that the spacers are in direct contact with the interconnect. The method further includes recessing the interconnect such that the uppermost surface of the interconnect remains above the uppermost surface of the recessed dielectric layer and is lower than an uppermost surface of the spacers.

An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.