A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing another layer of ILD on the contact; etching a first opening in the ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.

Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.

A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices. The seal ring structure includes a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers. Each of the hollow through-hole structure within an interlayer dielectric layer includes a through-hole disposed within one of the interlayer dielectric layers, a diffusion barrier layer formed at the bottom, sidewalls and the top of the through-hole, and a seed layer disposed on the diffusion barrier layer. The diffusion barrier layer and the seed layer cover the top of the through-hole so that the through-hole has a void to form the hollow through-hole structure.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.