A interconnect structure includes a lower metal, a dielectric layer, an upper metal, and a graphene layer. The dielectric layer laterally surrounds the lower metal. The upper metal is over the lower metal. The graphene layer is over a top surface of the upper metal and opposite side surfaces of the upper metal from a cross-sectional view.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer. The structure also includes a second feature formed in a second dielectric layer which has a second barrier layer disposed on vertical surfaces of the second dielectric layer and two vertical surfaces of the copper layer and a bottom surface of the first copper layer is disposed over the first barrier layer.

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MX.sub.n, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

A semiconductor device includes a conductive layer extending in a first direction, including a first surface, a second surface facing the first surface in a second direction intersecting the first direction, a third surface, and a fourth surface facing the third surface in a third direction intersecting the first direction and the second direction, and containing a first element which is at least one element of tungsten (W) or molybdenum (Mo); a first region disposed on a first surface side of the conductive layer, containing a second element which is at least one element of tungsten (W) or molybdenum (Mo), and a third element which is at least one element of sulfur (S), selenium (Se), or tellurium (Te), and including a first crystal; and a second region disposed on a second surface side of the conductive layer, containing the second element and the third element, and including a second crystal.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

Graphene is deposited on a metal surface of a semiconductor substrate at a deposition temperature compatible with back-end-of-line semiconductor processing. The graphene may be annealed at a temperature between the deposition temperature and a temperature sensitive limit of materials in the semiconductor substrate to improve film quality. Alternatively, the graphene may be treated by exposure to plasma with one or more oxidant species. The graphene may be encapsulated with an etch stop layer and hermetic barrier, where the etch stop layer includes a metal oxide deposited under conditions that do not change or that improve the film quality of the graphene. The graphene may be encapsulated with a hermetic barrier, where the hermetic barrier is deposited under conditions that do not damage the graphene.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.