A method for manufacturing a conductive laminate and a conductive laminate are provided. The method for manufacturing the conductive laminate includes steps of: providing a substrate having a surface; immersing the substrate into a modifying solution including a silane with a hydrophilic group to form a discontinuous modified layer on the surface of the substrate; forming a barrier layer on the surface of the substrate and the discontinuous modified layer, and forming a conductive layer on a surface of the barrier layer. The barrier layer includes a polymer, and the polymer is selected from the group consisting of: polyvinyl alcohol, polyvinylpyrrolidone, polyacrylic acid, polyethylene glycol, and any combination thereof.

The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

Described herein are a method and a power semiconductor device produced by the method. The power semiconductor device includes: transistor device structures formed in a semiconductor substrate; a structured metallization layer above the semiconductor substrate; a first passivation over the structured metallization layer; a second passivation on the first passivation; an opening in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation; a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.

An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.

Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

A semiconductor package with improved solderability at sidewall includes a chip, a molding compound encapsulating the chip, and multiple leads distributed at sidewalls of the semiconductor package. The leads are formed as a conductive layer that is electrically connected to bonding pads of the chip. Each of the leads has a stepped surface exposed from the molding compound, wherein the stepped surface is shaped by two sequentially overlapped photoresist layers. The stepped surface of each lead allows to accommodate more solder to enhance the reliability of a solder joint between the semiconductor and a printed circuit board. Therefore, the solder joints of the semiconductor package are easily inspected by automatic optical inspection (AOI) equipment.

Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).